ADUC7122 Analog Devices, ADUC7122 Datasheet - Page 81

• Manufacturer Part Number: ADUC7122
• Description: Precision Analog Microcontroller, 12-Bit Analog I/O, ARM7TDMI® MCU
• Manufacturer: Analog Devices

Specifications of ADUC7122

• Mcu Core: ARM7 TDMI
• Mcu Speed (mips): 40
• Sram (bytes): 8192Bytes
• Gpio Pins: 32
• Adc # Channels: 13

IRQSTAN Register
If IRQCONN[0] is asserted and IRQVEC is read, then one of
these bits is asserted. The bit that asserts depends on the prior-
ity of the IRQ. For example, if the IRQ is of Priority 0 then Bit 0
asserts; if it is Priority 1, then Bit 1 asserts. When a bit is set in
this register, all interrupts of that priority and lower are blocked.
To clear a bit in this register, all bits of a higher priority must
be cleared first. It is only possible to clear one bit at a time. For
example, if this register is set to 0x09, then writing 0xFF changes
the register to 0x08, and writing 0xFF a second time changes
the register to 0x00.
Name:
Address:
Default Value:
Access:
Table 137. IRQSTAN MMR Bit Designations
Bit
31:8
7:0
FIQVEC Register
The FIQ interrupt vector register, FIQVEC points to a memory
address containing a pointer to the interrupt service routine of
the currently active FIQ. This register should only be read when
an FIQ occurs and FIQ interrupt nesting has been enabled by
setting Bit 1 of the IRQCONN register.
Name:
Address:
Default Value:
Access:
Table 138. FIQVEC MMR Bit Designations
Bit
31:23
22:7
6:2
1:0
Name
Reserved
Type
Read only
R/W
Reserved
IRQSTAN
0xFFFF003C
0x00000000
Read and write
Description
These bits are reserved and should not be
written to.
Setting this bit to 1 enables nesting of FIQ
interrupts. Clearing this bit means no nesting
or prioritization of FIQs is allowed.
Initial
Value
0
0
0
0
FIQVEC
0xFFFF011C
0x00000000
Read only
Description
Always read as 0.
IRQBASE register value.
Highest priority FIQ source. This is
a value between 0 to 27, which
represents the possible interrupt
sources. For example, if the
highest currently active FIQ is
Timer1, then these bits are 00011.
Reserved bits.
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FIQSTAN Register
If IRQCONN[1] is asserted and FIQVEC is read then one of
these bits assert. The bit that asserts depends on the priority of
the FIQ. For example, if the FIQ is of Priority 0, then Bit 0
asserts; if it is Priority 1, then Bit 1 asserts.
When a bit is set in this register, all interrupts of that priority
and lower are blocked.
To clear a bit in this register, all bits of a higher priority must be
cleared first. It is only possible to clear one bit as a time. For
example, if this register is set to 0x09, then writing 0xFF
changes the register to 0x08 and writing 0xFF a second time
changes the register to 0x00.
Name:
Address:
Default Value:
Access:
Table 139. FIQSTAN MMR Bit Designations
Bit
31:8
7:0
External Interrupts (IRQ0 to IRQ5)
The ADuC7122 provides up to six external interrupt sources.
These external interrupts can be individually configured as level
or rising/falling edge triggered.
To enable the external interrupt source, the appropriate bit must
first be set in the FIQEN or IRQEN register. To select the
required edge or level to trigger on, the IRQCONE register
must be appropriately configured.
To properly clear an edge based external IRQ interrupt, set the
appropriate bit in the IRQCLRE register.
IRQCONE Register
Name:
Address:
Default Value:
Access:
Name
Reserved
FIQSTAN
0xFFFF013C
0x00000000
Read and write
IRQCONE
0xFFFF0034
0x00000000
Read and write
Description
These bits are reserved and should not be
written to.
Setting this bit to 1 enables nesting of FIQ
interrupts. Clearing this bit means no nesting
or prioritization of FIQs is allowed.
ADuC7122