ADUC7122 Analog Devices, ADUC7122 Datasheet - Page 63

• Manufacturer Part Number: ADUC7122
• Description: Precision Analog Microcontroller, 12-Bit Analog I/O, ARM7TDMI® MCU
• Manufacturer: Analog Devices

Specifications of ADUC7122

• Mcu Core: ARM7 TDMI
• Mcu Speed (mips): 40
• Sram (bytes): 8192Bytes
• Gpio Pins: 32
• Adc # Channels: 13

I
Name:
Address:
Default Value:
Access:
Function:
I
Name:
Address:
Default Value:
Access:
Function:
Table 104. I2CxADR0 MMR in 7-Bit Address Mode (Address = 0xFFFF0898, 0xFFFF0918, Default Value = 0x00)
Bit
7:1
0
Table 105. I2CxADR0 MMR in 10-Bit Address Mode
Bit
7:3
2:1
0
Table 106. I2CxADR1 MMR in 10-Bit Address Mode
Bit
7:0
Table 107. I2CxDIV MMR
Bit
15:8
7:0
2
2
C Address 0 Register
C Address 1 Register
Name
I2CADR
R/W
Name
I2CMADR
R/W
Name
I2CLADR
Name
DIVH
DIVL
I2C0ADR0, I2C1ADR0
0xFFFF0898, 0xFFFF0918
0x00, 0x00
Read/write
This 8-bit MMR holds the 7-bit slave address +
the read/write bit when the master begins
communicating with a slave.
I2C0ADR1, I2C1ADR1
0xFFFF089C, 0xFFFF091C
0x00, 0x00
Read/write
This 8-bit MMR is used in 10-bit addressing
mode only. This register contains the least
significant byte of the address.
Description
These bits contain the 7-bit address of the required slave device.
Bit 0 is the read/write bit.
When this bit = 1, a read sequence is requested.
When this bit = 0, a write sequence is requested.
Description
These bits must be set to [11110b] in 10-bit address mode.
These bits contain ADDR[9:8] in 10-bit addressing mode.
Read/write bit.
When this bit = 1, a read sequence is requested.
When this bit = 0, a write sequence is requested.
Description
These bits contain ADDR[7:0] in 10-bit addressing mode.
Description
These bits control the duration of the high period of SCLx.
These bits control the duration of the low period of SCLx.
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I
Name:
Address:
Default Value:
Access:
Function:
I
Name:
Address:
Default Value:
Access:
Function:
To generate a start byte followed by a normal address, first write
to I2CxSBYTE, then write to the address register (I2CxADRx).
This drives the byte written in I2CxSBYTE onto the bus fol-
lowed by a repeated start. This register can be used to drive any
byte onto the I
byte only, for example, 00000001).
2
2
C Start Byte Register
C Master Clock Control Register
2
C bus followed by a repeated start (not a start
I2C0DIV, I2C1DIV
0xFFFF08A4, 0xFFFF0924
0x1F1F, 0x1F1F
Read/write
This MMR controls the frequency of the I
clock generated by the master on to the SCL
pin. For further details, see the I
I2C0SBYTE, I2C1SBYTE
0xFFFF08A0, 0xFFFF0920
0x00, 0x00
Read/write
This MMR can be used to generate a start byte
at the start of a transaction.
ADuC7122
2
C section.
2
C