ADUC7122 Analog Devices, ADUC7122 Datasheet - Page 80

• Manufacturer Part Number: ADUC7122
• Description: Precision Analog Microcontroller, 12-Bit Analog I/O, ARM7TDMI® MCU
• Manufacturer: Analog Devices

Specifications of ADUC7122

• Mcu Core: ARM7 TDMI
• Mcu Speed (mips): 40
• Sram (bytes): 8192Bytes
• Gpio Pins: 32
• Adc # Channels: 13

ADuC7122
Table 133. IRQP1 MMR Bit Designations
Bit
31
30:28
27
26:24
23
22:20
19
18:16
15
14:12
11
10:8
7:3
2:0
IRQP2 Register
Name:
Address:
Default Value:
Access:
Table 134. IRQP2 MMR Bit Designations
Bit
31
30:28
27
26:24
23
22:20
19
18:16
15
14:12
11
10:8
7
6:4
3
2:0
Name
Reserved
I2C0MPI
Reserved
SPIPI
Reserved
UARTPI
Reserved
ADCPI
Reserved
Flash1PI
Reserved
Flash0PI
Reserved
PSMPI
Name
Reserved
PWMPI
Reserved
IRQ3PI
Reserved
IRQ2PI
Reserved
IRQ1PI
Reserved
IRQ0PI
Reserved
I2C1SPI
Reserved
I2C1MPI
Reserved
I2C0SPI
IRQP2
0xFFFF0028
0x00000000
Read and write
Description
Reserved bit.
A priority level of 0 to 7 can be set for the
I2C0 master.
Reserved bit.
A priority level of 0 to 7 can be set for the
SPI.
Reserved bit.
A priority level of 0 to 7 can be set for the
UART.
Reserved bit.
A priority level of 0 to 7 can be set for the
ADC interrupt source.
Reserved bit.
A priority level of 0 to 7 can be set for the
Flash Block 1 controller interrupt source.
Reserved bit.
A priority level of 0 to 7 can be set for the
Flash Block 0 controller interrupt source.
Reserved bits.
A priority level of 0 to 7 can be set for the
Power supply monitor interrupt source.
Description
Reserved bit.
A priority level of 0 to 7 can be set for PWM.
Reserved bit.
A priority level of 0 to 7 can be set for IRQ3.
Reserved bit.
A priority level of 0 to 7 can be set for IRQ2.
Reserved bit.
A priority level of 0 to 7 can be set for IRQ1.
Reserved bit.
A priority level of 0 to 7 can be set for IRQ0.
Reserved bit.
A priority level of 0 to 7 can be set for I2C1
slave.
Reserved bit.
A priority level of 0 to 7 can be set for I2C1
master.
Reserved bit.
A priority level of 0 to 7 can be set for I2C0
slave.
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IRQP3 Register
Name:
Address:
Default Value:
Access:
Table 135. IRQP3 MMR Bit Designations
Bit
31:15
14:12
11
10:8
7
6:4
3
2:0
IRQCONN Register
The IRQCONN register is the IRQ and FIQ control register. It
contains two active bits. The first enables nesting and prioritization
of IRQ interrupts and the other enables nesting and prioritiza-
tion of FIQ interrupts.
If these bits are cleared, then FIQs and IRQs can still be used,
but it is not possible to nest IRQs or FIQs. Neither is it possible
to set an interrupt source priority level. In this default state, an
FIQ does have a higher priority than an IRQ.
Name:
Address:
Default Value:
Access:
Table 136. IRQCONN MMR Bit Designations
Bit
31:2
1
0
Name
Reserved
ENFIQN
ENIRQN
Name
Reserved
PLA1PI
Reserved
PLA0PI
Reserved
IRQ5PI
Reserved
IRQ4PI
IRQP3
0xFFFF002C
0x00000000
Read and write
IRQCONN
0xFFFF0030
0x00000000
Read and write
Description
These bits are reserved and should not be
written to.
Setting this bit to 1 enables nesting of FIQ
interrupts. Clearing this bit means no nesting
or prioritization of FIQs is allowed.
Setting this bit to 1 enables nesting of IRQ
interrupts. Clearing this bit means no nesting
or prioritization of IRQs is allowed.
Description
Reserved bit.
A priority level of 0 to 7 can be set for PLA0.
Reserved bit.
A priority level of 0 to 7 can be set for PLA0.
Reserved bit.
A priority level of 0 to 7 can be set for IRQ5.
Reserved bit.
A priority level of 0 to 7 can be set for IRQ4.