ADUC7122 Analog Devices, ADUC7122 Datasheet - Page 60

• Manufacturer Part Number: ADUC7122
• Description: Precision Analog Microcontroller, 12-Bit Analog I/O, ARM7TDMI® MCU
• Manufacturer: Analog Devices

Specifications of ADUC7122

• Mcu Core: ARM7 TDMI
• Mcu Speed (mips): 40
• Sram (bytes): 8192Bytes
• Gpio Pins: 32
• Adc # Channels: 13

ADuC7122
Master Mode
In master mode, the I2CADR0 register is programmed with the
I
In 7-bit address mode, I2CADR0[7:1] are set to the device
address. I2CADR0[0] is the read/write bit.
In 10-bit address mode, the 10-bit address is created as follows:
I2CADR0[7:3] must be set to 11110b.
I2CADR0[2:1] = Address Bits[9:8].
I2CADR1[7:0] = Address Bits[7:0].
I2CADR0[0] is the read/write bit.
Table 101. I2CxMCTL MMR Bit Designations
Bit
15:9
8
7
6
5
4
3
2
1
0
2
C address of the device.
Name
I2CMRENI
I2CMSEN
I2CMCENI
I2CNACKENI
I2CALENI
I2CMTENI
I2CILEN
I2CBD
I2CMEN
Description
Reserved. These bits are reserved and should not be written to.
I
Set this bit to enable an interrupt on detecting a stop condition on the I
Clear this bit to disable the interrupt source.
I
Set this bit to enable interrupts when the I
Clear this bit to disable the interrupt source.
I
Set this bit to enable interrupts when the I
Clear this bit to disable the interrupt source.
I
Set this bit to enable interrupts when the I
Clear this bit to disable the interrupt source.
I
Set this bit to enable interrupts when the I
Cleared by user to disable interrupts when the I
I
Set this bit to 1 to enable clock stretching. When SCL is low, setting this bit forces the device to hold SCL low until
I2CMSEN is cleared. If SCL is high, setting this bit forces the device to hold SCL low after the next falling edge.
Clear this bit to disable clock stretching.
I
Set this bit to enable loopback test mode. In this mode, the SCL and SDA signals are connected internally to their
respective input signals.
Cleared by user to disable loopback mode.
I
Set this bit to allow the device to compete for control of the bus even if another device is currently driving a start
condition.
Clear this bit to back off (wait) until the I
I
Set by user to enable I
Cleared disable I
2
2
2
2
2
2
2
2
2
C transmission complete interrupt enable bit.
C NACK received interrupt enable bit.
C arbitration lost interrupt enable bit.
C transmit interrupt enable bit.
C receive interrupt enable bit.
C master SCL stretch enable bit.
C internal loopback enable.
C master backoff disable bit.
C master enable bit.
2
C master mode.
2
C master mode.
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2
C bus becomes free.
2
2
2
2
C master receives a NACK.
C master has lost in trying to gain control of the I
C master has transmitted a byte.
C master receives data.
2
C master is receiving data.
I
The I
These are described in the following section.
I
I
Name:
Address:
Default Value:
Access:
Function:
2
2
2
C Master Registers
C REGISTERS
C Master Control Register
2
C peripheral interface consists of a number of MMRs.
I2C0MCTL, I2C1MCTL
0xFFFF0880, 0xFFFF0900
0x0000, 0x0000
Read/write
This 16-bit MMR configures I
master mode.
2
C bus.
2
C bus.
2
C peripheral in