ADUC7122 Analog Devices, ADUC7122 Datasheet - Page 28

• Manufacturer Part Number: ADUC7122
• Description: Precision Analog Microcontroller, 12-Bit Analog I/O, ARM7TDMI® MCU
• Manufacturer: Analog Devices

Specifications of ADUC7122

• Mcu Core: ARM7 TDMI
• Mcu Speed (mips): 40
• Sram (bytes): 8192Bytes
• Gpio Pins: 32
• Adc # Channels: 13

ADuC7122
ADC TRANSFER FUNCTION
Pseudo Differential and Single-Ended Modes
In pseudo differential or single-ended mode, the input range is
0 V to V
differential and single-ended modes with
The ideal code transitions occur midway between successive
integer LSB values (that is, 1/2 LSB, 3/2 LSBs, 5/2 LSBs, …,
FS – 3/2 LSBs). The ideal input/output transfer characteristic is
shown in Figure 13.
Fully Differential Mode
The amplitude of the differential signal is the difference between
the signals applied to the V
V
mum amplitude of the differential signal is, therefore, −V
+V
(CM). The common mode is the average of the two signals
(V
are centered on. This results in the span of each input being CM
± V
varies with V
The output coding is twos complement in fully differential
mode with 1 LSB = 2 V
when V
shifted by one to the right, which allows the result in ADCDAT
to be declared as a signed integer when writing C code. The
designed code transitions occur midway between successive
integer LSB values (that is, 1/2 LSB, 3/2 LSBs, 5/2 LSBs, …,
FS − 3/2 LSBs). The ideal input/output transfer characteristic is
shown in Figure 14.
IN−
IN+
REF
REF
) of the currently enabled differential channel. The maxi-
1 LSB = FS/4096 or
2.5 V/4096 = 0.61 mV or
610 μV when V
1111 1111 1111
1111 1111 1110
1111 1111 1101
1111 1111 1100
0000 0000 0011
0000 0000 0010
0000 0000 0001
0000 0000 0000
Figure 13. ADC Transfer Function in Pseudo Differential Mode or
+ V
/2. This voltage must be set up externally, and its range
p-p (2 × V
REF
REF
IN−
. The output coding is straight binary in pseudo
= 2.5 V. The output result is ±11 bits, but this is
)/2, and is, therefore, the voltage that the two inputs
REF
(see the Driving the Analog Inputs section).
REF
0V
). This is regardless of the common mode
REF
1LSB
1LSB =
REF
= 2.5 V
Single-Ended Mode
/4096 or 2 × 2.5 V/4096 = 1.22 mV
IN+
4096
FS
and V
VOLTAGE INPUT
IN−
inputs (that is, V
+FS – 1LSB
IN+
REF
−
to
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ADC Input Channels
The ADuC7122 provides 11 fixed gain ADC input pins. Each of
these pins can be separately configured as a differential input
pair, single-ended input, or positive side pseudo differential input
(the negative side must be the AINCM channel). The buffer and
ADC are configured independently from input channel selec-
tion. Note that the input range of the ADC input buffer is from
0.15 V to AV
range, the input buffer must be bypassed.
The ADC mux can be configured to select an internal channel
like IOVDD_MON or the temperature sensor. When convert-
ing on an internal channel, the input buffer must be enabled.
In addition, an on-chip diode can be selected to provide chip
temperature monitoring. The ADC can also select V
AGND as the input for calibration purposes.
PGA and Input Buffer
The ADuC7122 contains two programmable gain channels that
operate in pseudo differential mode. The PGA is a one-stage
positive gain amplifier that is able to accept an input from 0.1 V
to AV
PGA is designed to handle 10 mV minimum input.
The gain of the PGA is from 1 to 5 with 32 linear steps. The
PGA cannot be bypassed for the PADC0 and PADC1 channels.
The PGAs use a PMOS input to minimize nonlinearity and
noise. The input level for PGA is limited from AV
0.1 V to make sure the amplifiers are not saturated. The input
buffer is a rail-to-rail buffer. It can accept signals from 0.15 V
to AV
independently.
To minimize noise, the PADC input buffer can be bypassed.
PADCxN is driven by a buffer to 0.15 V to keep the PGA from
saturation when the input current drops to 0. The buffer can be
disabled by setting ADCCON[14] so that the PADCxN can be
connected to GND as well.
The PADCx channels are only specified to operate in pseudo
differential mode and this assumes the negative input is close
to ground.
SIGN
BIT
0 1111 1111 1110
0 1111 1111 1100
0 1111 1111 1010
0 0000 0000 0001
0 0000 0000 0000
1 1111 1111 1110
1 0000 0000 0100
1 0000 0000 0010
1 0000 0000 0000
DD
DD
− 1.2 V. The PGA output can swing up to 2.5 V. The
− 0.15 V. Each of the input buffers can be bypassed
Figure 14. ADC Transfer Function in Differential Mode
DD
− 0.15 V. If the input signal range exceeds this
–V
REF
1LSB =
+ 1LSB
2 × V
VOLTAGE INPUT (V
4096
REF
0LSB
IN
+ – V
IN
+V
–)
DD
REF
− 1.2 V to
REF
– 1LSB
and