ADUC7122 Analog Devices, ADUC7122 Datasheet - Page 75

• Manufacturer Part Number: ADUC7122
• Description: Precision Analog Microcontroller, 12-Bit Analog I/O, ARM7TDMI® MCU
• Manufacturer: Analog Devices

Specifications of ADUC7122

• Mcu Core: ARM7 TDMI
• Mcu Speed (mips): 40
• Sram (bytes): 8192Bytes
• Gpio Pins: 32
• Adc # Channels: 13

Table 119. PLAIRQ Register
Name
PLAIRQ
PLAIRQ enables IRQ0 and/or IRQ1 and selects the source
of the IRQ.
Table 120. PLAIRQ MMR Bit Descriptions
Bit
15:13
12
11:8
7:5
4
3:0
Table 121. PLAADC Register
Name
PLAADC
PLAADC is the PLA source for the ADC start conversion signal.
Table 122. PLAADC MMR Bit Descriptions
Bit
31:5
4
3:0
Value
1
0
0000
0001
1111
Value
1
0
0000
0001
1111
0000
0001
1111
Address
0xFFFF0B44
Address
0xFFFF0B48
Description
Reserved.
ADC start conversion enable bit.
Set by the user to enable ADC start
conversion from PLA.
Cleared by the user to disable ADC start
conversion from PLA.
ADC start conversion source.
PLA Element 0.
PLA Element 1.
PLA Element 15.
Description
Reserved.
PLA IRQ1 enable bit.
Set by the user to enable the IRQ1 output
from PLA.
Cleared by the user to disable IRQ1
output from PLA.
PLA IRQ1 source.
PLA Element 0.
PLA Element 1.
PLA Element 15.
Reserved.
PLA IRQ0 enable bit.
Set by the user to enable IRQ0 output
from PLA.
Cleared by the user to disable IRQ0
output from PLA.
PLA IRQ0 source.
PLA Element 0.
PLA Element 1.
PLA Element 15.
Default Value
0x00000000
Default Value
0x00000000
Access
R/W
Access
R/W
Rev. 0 | Page 75 of 96
Table 123. PLADIN Register
Name
PLADIN
Table 124. PLADIN MMR Bit Descriptions
Bit
31:16
15:0
PLADIN is a data input MMR for PLA.
Table 125. PLADOUT Register
Name
PLADOUT
PLADOUT is a data output MMR for PLA. This register is
always updated.
Table 126. PLADOUT MMR Bit Descriptions
Bit
31:16
15:0
Table 127. PLACLK Register
Name
PLACLK
PLACLK is a PLA lock option. Bit 0 is written only once. When
set, it does not allow modification of any of the PLA MMRs,
except PLADIN. A PLA tool is provided in the development
system to easily configure the PLA.
Description
Reserved.
Output bit from Element 15 to Element 0.
Address
0xFFFF0B4C
Address
0xFFFF0B50
Address
0xFFFF0B40
Description
Reserved.
Input bit to Element 15 to Element 0.
Default Value
0x00000000
Default Value
0x00000000
Default Value
0x00
ADuC7122
Access
R/W
Access
R
Access
W