ADUC7122 Analog Devices, ADUC7122 Datasheet - Page 76

• Manufacturer Part Number: ADUC7122
• Description: Precision Analog Microcontroller, 12-Bit Analog I/O, ARM7TDMI® MCU
• Manufacturer: Analog Devices

Specifications of ADUC7122

• Mcu Core: ARM7 TDMI
• Mcu Speed (mips): 40
• Sram (bytes): 8192Bytes
• Gpio Pins: 32
• Adc # Channels: 13

ADuC7122
INTERRUPT SYSTEM
There are 27 interrupt sources on the ADuC7122 that are con-
trolled by the interrupt controller. All interrupts are generated
from the on-chip peripherals, except for the software interrupt
(SWI), which is programmable by the user. The ARM7TDMI
CPU core only recognizes interrupts as one of two types: a
normal interrupt request (IRQ) and a fast interrupt request
(FIQ). All the interrupts can be masked separately.
The control and configuration of the interrupt system is
managed through a number of interrupt-related registers. The
bits in each IRQ and FIQ register represent the same interrupt
source, as described in Table 128.
Table 128. IRQ/FIQ
Bit
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
1
Applies to IRQEN, FIQEN, IRQCLR, FIQCLR, IRQSTA, and FIQSTA registers.
Description
All interrupts OR’ed (FIQ only)
Software interrupt
Timer0
Timer1
Timer2 or wake-up timer
Timer3 or watchdog timer
Timer4
Reserved
PSM
Undefined
Flash Control 0
Flash Control 1
ADC
UART
SPI
I2C0 master IRQ
I2C0 slave IRQ
I2C1 master IRQ
I2C1 slave IRQ
XIRQ0 (GPIO IRQ0 )
XIRQ1 (GPIO IRQ1)
XIRQ2 (GPIO IRQ2 )
XIRQ3 (GPIO IRQ3)
PWM
XIRQ4 (GPIO IRQ4 )
XIRQ5 (GPIO IRQ5)
PLA IRQ0
PLA IRQ1
1
MMRs Bit Designations
Rev. 0 | Page 76 of 96
Comments
This bit is set if any FIQ is active
User programmable interrupt source
General-Purpose Timer0
General-Purpose Timer1
General-Purpose Timer2 or wake-up timer
General-Purpose Timer3 or watchdog timer
General-Purpose Timer4
Reserved
Power supply monitor
This bit is not used
Flash controller for Block 0 interrupt
Flash controller for Block 1 interrupt
ADC interrupt source bit
UART interrupt source bit
SPI interrupt source bit
I
I
I
I
External Interrupt 0
External Interrupt 1
External Interrupt 2
External Interrupt 3
PWM trip interrupt source bit
External Interrupt 4
External Interrupt 5
PLA Block 0 IRQ bit
PLA Block 1 IRQ bit
2
2
2
2
C master interrupt source bit
C slave interrupt source bit
C master interrupt source bit
C slave interrupt source bit
The ADuC7122 contains a vectored interrupt controller (VIC)
that supports nested interrupts up to eight levels. The VIC also
allows the programmer to assign priority levels to all interrupt
sources. Interrupt nesting needs to be enabled by setting the
ENIRQN bit in the IRQCONN register. A number of extra
MMRs are used when the full vectored interrupt controller is
enabled.
IRQSTA/FIQSTA should be saved immediately upon entering
the interrupt service routine (ISR) to ensure that all valid
interrupt sources are serviced.