ADUC7122 Analog Devices, ADUC7122 Datasheet - Page 64

• Manufacturer Part Number: ADUC7122
• Description: Precision Analog Microcontroller, 12-Bit Analog I/O, ARM7TDMI® MCU
• Manufacturer: Analog Devices

Specifications of ADUC7122

• Mcu Core: ARM7 TDMI
• Mcu Speed (mips): 40
• Sram (bytes): 8192Bytes
• Gpio Pins: 32
• Adc # Channels: 13

ADuC7122
I
I
Name:
Address:
Default Value:
Access:
Function:
Table 108. I2CxSCTL MMR Bit Designations
Bit
15:11
10
9
8
7
6
5
4
3
2
2
C Slave Registers
C Slave Control Register
Name
I2CSTXENI
I2CSRXENI
I2CSSENI
I2CNACKEN
I2CSSEN
I2CSETEN
I2CGCCLR
I2CHGCEN
Set this bit to NACK the next byte in the transmission sequence.
Clear this bit to let the hardware control the ACK/NACK sequence.
I
Clear this bit to disable clock stretching.
I
I
Writing a 1 to this bit clears the general call status (I2CGC) and ID (I2CGCID[1:0]) bits in the I2CxSSTA register.
Clear this bit at all other times.
Set this bit to 1 to enable clock stretching. When SCLx is low, setting this bit forces the device to hold SCLx low until
I2CSSEN is cleared. If SCL is high, setting this bit forces the device to hold SCLx low after the next falling edge.
Setting this bit enables a transmit request interrupt just after the positive edge of SCLx during the read bit
transmission.
Clear this bit to enable a transmit request interrupt just after the negative edge of SCLx during the read bit
transmission.
Description
Reserved bits.
Slave transmit interrupt enable bit.
Set this bit to enable an interrupt after a slave transmits a byte.
Clear this interrupt source.
Slave receive interrupt enable bit.
Set this bit to enable an interrupt after the slave receives data.
Clear this interrupt source.
I
Set this bit to enable an interrupt on detecting a stop condition on the I
Clear this interrupt source.
I
I
Hardware general call enable. When this bit and Bit 2 are set, and having received a general call (Address 0x00) and a
data byte, the device checks the contents of I2CxALT against the receive register. If the contents match, the device
has received a hardware general call. This method is used if a device needs urgent attention from a master device
without knowing which master it needs to turn to. This is a broadcast message to all master devices on the bus. The
ADuC7122 watches for these addresses. The device that requires attention embeds its own address into the
message. All masters listen, and the one that can handle the device contacts its slave and acts appropriately.
The LSB of the I2CxALT register should always be written to 1, as per the I
Set this bit and I2CGCEN to enable hardware general call recognition in slave mode.
Clear this bit to disable recognition of hardware general call commands.
2
2
2
2
2
2
C slave SCLx stretch enable bit.
C early transmit interrupt enable bit.
C general call status and ID clear bit.
C stop condition detected interrupt enable bit.
C NACK enable bit.
C hardware general call enable.
I2C0SCTL, I2C1SCTL
0xFFFF08A8, 0xFFFF0928
0x0000, 0x000
Read/write
This 16-bit MMR configures the I
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2
C peripheral in slave mode.
2
C bus.
2
C January 2000 bus specification.