ADUC7122 Analog Devices, ADUC7122 Datasheet - Page 18

• Manufacturer Part Number: ADUC7122
• Description: Precision Analog Microcontroller, 12-Bit Analog I/O, ARM7TDMI® MCU
• Manufacturer: Analog Devices

Specifications of ADUC7122

• Mcu Core: ARM7 TDMI
• Mcu Speed (mips): 40
• Sram (bytes): 8192Bytes
• Gpio Pins: 32
• Adc # Channels: 13

ADuC7122
Pin No.
A9
A11
A10
B12
B11
B10
B9
M1
M6
L1
M7
M12
B6
L12
C7
B7
G1
G12
F1
F12
H1
J1
H12
J12
G2
H2
D10
C10
F10
E10
1
I = input, I/O = input/output, AI/O = analog input/output, NC = no connect, AO = analog output, AI = analog input, DI = digital input, DO = digital output, S = supply.
Mnemonic
NC
NC
NC
NC
NC
AGND
AGND
AGND
AGND
AVDD
AVDD
AGND
AGND
AVDD
NC
REG_PWR
LVDD
LVDD
DGND
DGND
IOVDD
IOGND
IOVDD
IOGND
XTALO
XTALI
TDO/P1.3/PLAO[14]
TDI/P1.2/PLAO[15]
TCK
TMS
S
S
Type
NC
NC
NC
NC
NC
S
S
S
S
S
S
S
S
S
NC
S
S
S
S
S
S
S
DO
DI
DO
DI
DI
DI
1
Description
No Connect.
No Connect.
No Connect.
No Connect.
No Connect.
Analog Ground.
Analog Ground.
Analog Ground.
Analog Ground.
Analog Supply (3.3 V).
Analog Supply (3.3 V).
Analog Ground.
Analog Ground.
Analog Supply (3.3 V).
No Connect.
Output of 2.5 V On-Chip Regulator. A 470 nF capacitor to DGND must be connected to
this pin.
Output of 2.6 V On-Chip LDO Regulator. A 470 nF capacitor to DGND must be
connected to this pin.
Output of 2.6 V On-Chip LDO Regulator. A 470 nF capacitor to DGND must be
connected to this pin.
Digital ground.
Digital ground.
3.3 V GPIO Supply.
3.3 V GPIO Ground.
3.3 V GPIO Supply.
3.3 V GPIO Ground.
Output from the Crystal Oscillator Inverter. If an external crystal is not being used, this
pin can be left unconnected.
Input to the Crystal Oscillator Inverter and Input to the Internal Clock Generator
Circuits. If an external crystal is not being used, this pin should be connected to the
DGND system ground.
JTAG Test Port Output, Test Data Out (TDO). Debug and download access.
General-Purpose Input and Output Port 1.3 (P1.3).
Output of PLA Element 14 (PLAO[14]). This pin should not be used as a GPIO when
debugging via the JTAG interface.
JTAG Test Port Input, Test Data In (TDI). Debug and download access.
General-Purpose Input and Output Port 1.2 (P1.2).
Output of PLA Element 15 (PLAO[15]). This pin should not be used as a GPIO when
debugging via the JTAG interface.
JTAG Test Port Input, Test Clock. Debug and download access.
JTAG Test Port Input, Test Mode Select. Debug and download access.
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