ADUC7122 Analog Devices, ADUC7122 Datasheet - Page 5

• Manufacturer Part Number: ADUC7122
• Description: Precision Analog Microcontroller, 12-Bit Analog I/O, ARM7TDMI® MCU
• Manufacturer: Analog Devices

Specifications of ADUC7122

• Mcu Core: ARM7 TDMI
• Mcu Speed (mips): 40
• Sram (bytes): 8192Bytes
• Gpio Pins: 32
• Adc # Channels: 13

SPECIFICATIONS
AV
Table 1.
Parameter
ADC CHANNEL SPECIFICATIONS
ENDPOINT ERRORS
DYNAMIC PERFORMANCE
ANALOG INPUT
PADC0 INPUT
PADC1 INPUT
Offset Error
Offset Error Match
Gain Error
Gain Error Match
Signal-to-Noise Ratio (SNR)
Total Harmonic Distortion (THD)
Peak Harmonic or Spurious Noise
Channel-to-Channel Crosstalk
Input Voltage Ranges
Leakage Current
Input Capacitance
Input Capacitance
Full Scale Input Range
Input Leakage at PADC0P
Resolution
Gain Error
Gain Drift
Offset
Offset Drift
PADC0P Compliant Range
Full Scale Input Range
Input Leakage at PADC1P
Resolution
Gain Error
Gain Drift
Offset
Offset Drift
PADC1P Compliant Range
ADC Power-Up Time
DC Accuracy
DD
Resolution
Integral Nonlinearity
Differential Nonlinearity
DC Code Distribution
Differential Mode
Single-Ended Mode
Single-Ended Mode
= IOV
4
4
4
4
4
4
DD
4
4
1, 2
= 3.0 V to 3.6 V, V
5
4
4
3, 4
REF
= 2.5 V internal reference, f
Min
12
0.15
20
11
0.1
10.6
11
0.1
Typ
5
±0.6
±0.5
1
±2
±1
±2
±1
69
−78
−75
−80
±0.2
20
20
0.15
3
30
0.15
3
30
Rev. 0 | Page 5 of 96
Max
±2
+1.4/−0.99
±5
±5
V
0 to V
AV
1000
2
1
50
6
60
AV
700
2
1
50
6
60
AV
CM
CORE
DD
DD
DD
6
± V
− 1.5
− 1.2
− 1.2
REF
= 41.78 MHz, T
REF
/2
Unit
μs
Bits
LSB
LSB
LSB
LSB
LSB
LSB
LSB
dB
dB
dB
dB
V
V
V
μA
pF
pF
μA
nA
Bits
%
ppm/°C
nA
pA/°C
V
μA
nA
Bits
%
ppm/°C
nA
pA/°C
V
A
= −10°C to +95°C, unless otherwise noted.
Test Conditions/Comments
Eight acquisition clocks and f
2.5 V internal reference, not production tested
for PADC0/PADC1 channels
2.5 V internal reference, gauranteed monotonic
ADC input is a dc voltage
Internally unbuffered channels
f
unbuffered channels
Includes distortion and noise components
Measured on adjacent channels
See Table 35 and Table 36
Buffer bypassed
Buffer enabled
During ADC acquisition buffer bypassed
During ADC acquisition buffer enabled
28.3 kΩ resistor, PGA gain = 3; acquisition time =
6 μs, pseudo differential mode
0.1% accuracy, 5 ppm external resistor for I to V
PGA offset not included
53.5 kΩ resistor, PGA gain = 3; acquisition time =
6 μs, pseudo differential mode
0.1% accuracy, 5 ppm external resistor for I to V
PGA offset not included
IN
= 10 kHz sine wave, f
SAMPLE
= 1 MSPS internally
ADC
ADuC7122
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