ADUC7122 Analog Devices, ADUC7122 Datasheet - Page 24

• Manufacturer Part Number: ADUC7122
• Description: Precision Analog Microcontroller, 12-Bit Analog I/O, ARM7TDMI® MCU
• Manufacturer: Analog Devices

Specifications of ADUC7122

• Mcu Core: ARM7 TDMI
• Mcu Speed (mips): 40
• Sram (bytes): 8192Bytes
• Gpio Pins: 32
• Adc # Channels: 13

ADuC7122
Table 12. Timer Base Address = 0xFFFF0300
Address
0x0300
0x0304
0x0308
0x030C
0x0310
0x0314
0x0320
0x0324
0x0328
0x032C
0x0330
0x0340
0x0344
0x0348
0x034C
0x0360
0x0364
0x0368
0x036C
0x0380
0x0384
0x0388
0x038C
0x0390
Table 13. PLL Base Address = 0xFFFF0400
Address
0x0404
0x0408
0x040C
0x0410
0x0414
0x0418
Table 14. PSM Base Address = 0xFFFF0440
Address
0x0440
Table 15. Reference Base Address = 0xFFFF0480
Address
0x0480
Name
POWKEY1
POWCON
POWKEY2
PLLKEY1
PLLCON
PLLKEY2
Name
PSMCON
Name
REFCON
Name
T0LD
T0VAL0
T0VAL1
T0CON
T0CLRI
T0CAP
T1LD
T1VAL
T1CON
T1CLRI
T1CAP
T2LD
T2VAL
T2CON
T2CLRI
T3LD
T3VAL
T3CON
T3CLRI
T4LD
T4VAL
T4CON
T4CLRI
T4CAP
Byte
2
2
4
4
1
2
4
4
4
1
4
4
4
4
1
2
2
2
1
4
4
4
1
4
Byte
1
Byte
2
Byte
2
1
2
2
1
2
Access Type
R/W
R
R
R/W
W
R
R/W
R
R/W
W
R
R/W
R
R/W
W
R/W
R
R/W
W
R/W
R
R/W
W
R
Access Type
R/W
Access Type
R/W
Access Type
W
R/W
W
W
R/W
W
Cycle
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
Cycle
2
Cycle
2
Cycle
2
2
2
2
2
2
Rev. 0 | Page 24 of 96
Table 16. ADC Base Address = 0xFFFF0500
Address
0x0500
0x0504
0x0508
0x050C
0x0510
0x0514
0x0520
Table 17. DAC Base Address = 0xFFFF0580
Address
0x0580
0x0584
0x0588
0x058C
0x0590
0x0594
0x0598
0x059C
0x05A0
0x05A4
0x05A8
0x05AC
0x05B0
0x05B4
0x05B8
0x05BC
0x05C0
0x05C4
0x05C8
0x05CC
0x05D0
0x05D4
0x05D8
0x05DC
Name
DAC0CON
DAC0DAT
DAC1CON
DAC1DAT
DAC2CON
DAC2DAT
DAC3CON
DAC3DAT
DAC4CON
DAC4DAT
DAC5CON
DAC5DAT
DAC6CON
DAC6DAT
DAC7CON
DAC7DAT
DAC8CON
DAC8DAT
DAC9CON
DAC9DAT
DAC10CON
DAC10DAT
DAC11CON
DAC11DAT
Name
ADCCON
ADCCP
ADCCN
ADCSTA
ADCDAT
ADCRST
PGA_GN
Byte
4
1
1
1
4
1
2
Byte
2
4
2
4
2
4
2
4
2
4
2
4
2
4
2
4
2
4
2
4
2
4
2
4
Access Type
R/W
R/W
R/W
R
R
W
R/W
Access Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Cycle
2
2
2
2
2
2
2
Cycle
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2