ATxmega64A1 Atmel Corporation, ATxmega64A1 Datasheet - Page 90
ATxmega64A1
Manufacturer Part Number
ATxmega64A1
Description
Manufacturer
Atmel Corporation
Specifications of ATxmega64A1
Flash (kbytes)
64 Kbytes
Pin Count
100
Max. Operating Frequency
32 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
78
Ext Interrupts
78
Usb Speed
No
Usb Interface
No
Spi
12
Twi (i2c)
4
Uart
8
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
4
Resistive Touch Screen
No
Dac Channels
4
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
AES/DES
Sram (kbytes)
4
Eeprom (bytes)
2048
Self Program Memory
YES
External Bus Interface
1
Dram Memory
sdram
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.6 to 3.6
Operating Voltage (vcc)
1.6 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
8
Output Compare Channels
24
Input Capture Channels
24
Pwm Channels
24
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATxmega64A1-AU
Manufacturer:
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Quantity:
135
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Part Number:
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Manufacturer:
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7.10.5
7.10.6
8077H–AVR–12/09
RC32KCAL - 32 KHz Oscillator Calibration Register
PLLCTRL - PLL Control Register
• Bit 7:2 - Reserved
These bits are reserved and will always be read as zero. For compatibility with future devices,
always write these bits to zero when this register is written.
• Bit 1 - XOSCFDIF: Failure Detection Interrupt Flag
If the external clock source oscillator failure monitor is enabled, the XOSCFDIF is set when a
failure is detected. Writing logic one to this location will clear XOSCFDIF. Note that having this
flag set will not stop the fail monitor circuit to request a new interrupt if the external clock sources
are re-enabled and a new failure occurs.
• Bit 0 - XOSCFDEN: Failure Detection Enable
Setting this bit will enable the failure detection monitor, and a Non-Maskable Interrupt will be
issued when the XOSCFDIF is set.
This bit is protected by the Configuration Change Protection mechanism, refer to
”Configuration Change Protection” on page 12
will only be disabled by a reset.
• Bit 7:0 - RC32KCAL[7:0]: 32.768 KHz Internal Oscillator Calibration Register
This register is used to calibrate the Internal 32.768 kHz Oscillator. A factory-calibrated value is
loaded from the signature row of the device and written to this register during reset, giving an
oscillator frequency close to 32.768 kHz. The register can also be written from software to cali-
brate the oscillator frequency during normal operation.
• Bit 7:6 - PLLSRC[1:0]: Clock Source
The PLLSRC bits select the input source for the PLL according to
Bit
+0x04
Read/Write
Initial Value
Bit
+0x05
Read/Write
Initial Value
R/W
7
x
R/W
7
0
PLLSRC[1:0]
R/W
6
x
R/W
6
0
R/W
5
x
R
5
0
-
R/W
4
RC32KCAL[7:0]
x
R/W
4
0
for details. Once enabled, the failure detection
R/W
3
x
R/W
3
0
PLLFAC[4:0]
R/W
2
x
R/W
2
0
Table 7-7 on page
R/W
1
x
R/W
1
0
XMEGA A
R/W
0
x
R/W
0
0
Section 3.12
91.
RC32KCAL
PLLCTRL
90
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