ATxmega64A1 Atmel Corporation, ATxmega64A1 Datasheet - Page 319
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ATxmega64A1
Manufacturer Part Number
ATxmega64A1
Description
Manufacturer
Atmel Corporation
Specifications of ATxmega64A1
Flash (kbytes)
64 Kbytes
Pin Count
100
Max. Operating Frequency
32 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
78
Ext Interrupts
78
Usb Speed
No
Usb Interface
No
Spi
12
Twi (i2c)
4
Uart
8
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
4
Resistive Touch Screen
No
Dac Channels
4
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
AES/DES
Sram (kbytes)
4
Eeprom (bytes)
2048
Self Program Memory
YES
External Bus Interface
1
Dram Memory
sdram
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.6 to 3.6
Operating Voltage (vcc)
1.6 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
8
Output Compare Channels
24
Input Capture Channels
24
Pwm Channels
24
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATxmega64A1-AU
Manufacturer:
Atmel
Quantity:
135
Company:
Part Number:
ATxmega64A1U-AU
Manufacturer:
ATMEL
Quantity:
953
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26.6
26.7
26.8
26.9
8077H–AVR–12/09
DAC clock
Timing constraints
Low Power mode
Calibration
Figure 26-2. DAC output model
Notes:
The DAC is clocked from the Peripheral clock (clk
refresh rate in S/H mode is configured relative to the Peripheral Clock.
Some timing constraints are given to make sure the DAC operates correctly. The timing con-
straints are relative to the frequency of the Peripheral clock. Not meeting the timing constraints
may reduce the accuracy of DAC conversions.
To reduce the power consumption in DAC conversions, the DAC may be set in a Low Power
mode. In Low Power mode, the DAC is turned off between each conversion. Conversion time
will be longer if new conversions are started in this mode. To put the DAC into low power mode,
you need to set the bit 1 in CTRLA register (called DACCRA).
To achieve optimal accuracy, it is possible to calibrate both gain and offset error in the DAC.
There is a 7-bit calibration value for gain adjustment and a 7-bit calibration value for offset
adjustment.
To get the best calibration result it is recommended to use the same VREF, output channel
selection, sampling time, and refresh interval when calibrating as will be used in normal DAC
operation. The theoretical transfer function for the DAC was shown in
Including errors, the DAC output value can be expressed as:
In an ideal DAC, gain is 1 and offset is 0.
V
• The DAC sampling time is the time interval between a completed channel conversion until
• The DAC refresh time is the time interval between each time a channel is updated in dual
DAC voltage
DACxX
starting a new conversion. This should not be less than 1 µs for single channel mode and 1.5
µs for dual channel (S/H) mode.
channel mode. This should not be more than 30 µs.
1. The DAC R
2. The DAC R
=
gain
⋅
CHnDATA
--------------------------- -
0xFFF
channel
channel
Buffer
+
is ~300 Ω for ATxmegaA3 and ATxmegaA4
is ~850 Ω for ATxmegaA1
offset
DAC out
PER
) directly. The DAC conversion interval and
R
R
feedback
channel
”Overview” on page
XMEGA A
DAC output
317.
319
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