ATxmega64A1 Atmel Corporation, ATxmega64A1 Datasheet - Page 368

• Manufacturer Part Number: ATxmega64A1
• Manufacturer: Atmel Corporation

Specifications of ATxmega64A1

• Flash (kbytes): 64 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 78
• Ext Interrupts: 78
• Usb Speed: No
• Usb Interface: No
• Spi: 12
• Twi (i2c): 4
• Uart: 8
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 4
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 4
• Eeprom (bytes): 2048
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 8
• Output Compare Channels: 24
• Input Capture Channels: 24
• Pwm Channels: 24
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

30.11.1.2
8077H–AVR–12/09
Addressing the Flash
Figure 30-1. Read-While-Write vs. No Read-While-Write
The Z-pointer is used to hold the Flash memory address for read and write access. The Z pointer
consists of the ZL and ZH registers in the register file, and RAMPZ Register for devices with
more than 64K bytes for Flash memory. For more details on the Z-pointer refer to
and Z- Registers” on page
Since the Flash is word accessed and organized in pages, the Z-pointer can be treated as hav-
ing two sections. The least significant bits address the words within a page, while the most
significant bits address the page within the Flash. This is shown in
word address in the page (FWORD) is held by the bits [WORDMSB:1] in the Z-pointer. The
remaining bits [PAGEMSB:WORDMSB+1] in the Z-pointer holds the Flash page address
(FPAGE). Together FWORD and FPAGE holds an absolute address to a word in the Flash.
For Flash read operations (ELPM and LMP), one byte is read at a time. For this the Least Signif-
icant Bit (bit 0) in the Z-pointer is used to select the low byte or high byte in the word address. If
this bit is 0, the low byte is read, and if this bit is 1 the high byte is read.
The size of FWORD and FPAGE will depend on the page and flash size in the device, refer to
each device data sheet for details on this.
Once a programming operation is initiated, the address is latched and the Z-pointer can be
updated and used for other operations.
Z-pointer
Adresses RWW
Section
Code Located in
NRWW Section Can
be Read During the
Operation
10.
Boot Loader Section -
No Read-While-Write
Application Section -
Read-While-Write
(NRWW)
(RWW)
Figure 30-2 on page
Z-pointer
Adresses NRWW
Section
CPU is Halted
During the Operation
XMEGA A
”The X-, Y-
369. The
368