ATxmega64A1 Atmel Corporation, ATxmega64A1 Datasheet - Page 219
ATxmega64A1
Manufacturer Part Number
ATxmega64A1
Description
Manufacturer
Atmel Corporation
Specifications of ATxmega64A1
Flash (kbytes)
64 Kbytes
Pin Count
100
Max. Operating Frequency
32 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
78
Ext Interrupts
78
Usb Speed
No
Usb Interface
No
Spi
12
Twi (i2c)
4
Uart
8
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
4
Resistive Touch Screen
No
Dac Channels
4
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
AES/DES
Sram (kbytes)
4
Eeprom (bytes)
2048
Self Program Memory
YES
External Bus Interface
1
Dram Memory
sdram
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.6 to 3.6
Operating Voltage (vcc)
1.6 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
8
Output Compare Channels
24
Input Capture Channels
24
Pwm Channels
24
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATxmega64A1-AU
Manufacturer:
Atmel
Quantity:
135
Company:
Part Number:
ATxmega64A1U-AU
Manufacturer:
ATMEL
Quantity:
953
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19.9.3
8077H–AVR–12/09
CTRLC - TWI Master Control Register C
• Bits 7:3 - Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always
write these bits to zero when this register is written.
• Bit 2 - ACKACT: Acknowledge Action
The Acknowledge Action (ACKACT) bit defines the master's acknowledge behavior in Master
Read mode. The Acknowledge Action is executed when a command is written to the CMD bits. If
SMEN in Control Register B is set, the Acknowledge Action is performed when the DATA regis-
ter is read.
Table 19-3
Table 19-3.
• Bit 1:0 - CMD[1:0]: Command
Writing the Command (CMD) bits triggers a master operation as defined by
CMD bits are strobe bits, and always read as zero. The Acknowledge Action is only valid in Mas-
ter Read mode (R). In Master Write mode (W), a command will only result in a Repeated START
or STOP condition. The ACKACT bit and the CMD bits can be written at the same time, and then
the Acknowledge Action will be updated before the command is triggered.
Table 19-4.
Writing a command to the CMD bits will clear the master interrupt flags and the CLKHOLD flag.
Bit
+0x02
Read/Write
Initial Value
CMD[1:0]
00
01
10
11
ACKACT
lists the acknowledge actions.
0
1
7
R
0
-
ACKACT Bit Description
CMD Bit Description
R
6
0
MODE
-
W
R
X
X
X
Action
Send ACK
Send NACK
R
5
0
-
Operation
Reserved
Execute Acknowledge Action succeeded by repeated START
condition
No operation
Execute Acknowledge Action succeeded by a byte receive
Execute Acknowledge Action succeeded by issuing a STOP
condition
R
4
0
-
R
3
0
-
ACKACT
R/W
2
0
R/W
1
0
CMD[1:0]
XMEGA A
Table
R/W
0
0
19-4. The
CTRLC
219
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