ATxmega64A1 Atmel Corporation, ATxmega64A1 Datasheet - Page 323
ATxmega64A1
Manufacturer Part Number
ATxmega64A1
Description
Manufacturer
Atmel Corporation
Specifications of ATxmega64A1
Flash (kbytes)
64 Kbytes
Pin Count
100
Max. Operating Frequency
32 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
78
Ext Interrupts
78
Usb Speed
No
Usb Interface
No
Spi
12
Twi (i2c)
4
Uart
8
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
4
Resistive Touch Screen
No
Dac Channels
4
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
AES/DES
Sram (kbytes)
4
Eeprom (bytes)
2048
Self Program Memory
YES
External Bus Interface
1
Dram Memory
sdram
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.6 to 3.6
Operating Voltage (vcc)
1.6 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
8
Output Compare Channels
24
Input Capture Channels
24
Pwm Channels
24
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATxmega64A1-AU
Manufacturer:
Atmel
Quantity:
135
Company:
Part Number:
ATxmega64A1U-AU
Manufacturer:
ATMEL
Quantity:
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8077H–AVR–12/09
Table 26-4
for longer conversion intervals during dual channel operation, a 50% increase in the number
peripheral clock cycles is automatically added.
Table 26-4.
The number of clock cycles selected multiplied with the period of the Peripheral clock gives the
minimum DAC conversion internal.
• Bits 3:0 - REFRESH[3:0]: DAC Channel Refresh Timing Control
These bits control time interval between each time a channel is refreshed in dual channel (S/H)
mode. The interval must be set relative to the Peripheral clock to avoid loosing accuracy of the
converted value.
Table 26-5
Table 26-5.
CONINTCAL[2:0]
REFRESH[3:0]
000
001
010
011
100
101
110
111
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
shows the available control settings as a number of peripheral clock cycles. To allow
shows the available timing control settings as a number of peripheral clock cycles.
DAC Conversion Interval
DAC Channel refresh control selection
Group Configuration
Group Configuration
128CLK
16CLK
32CLK
64CLK
1CLK
2CLK
4CLK
8CLK
16384CLK
32768CLK
65536CLK
1024CLK
2048CLK
4096CLK
8192CLK
128CLK
256CLK
512CLK
16CLK
32CLK
64CLK
clk
channel operation
PER
cycles for Single
128 CLK
16 CLK
32 CLK
64 CLK
1 CLK
2 CLK
4 CLK
8 CLK
clk
PER
cycles refresh interval
16384 CLK
32768 CLK
65536 CLK
1024 CLK
2048 CLK
4096 CLK
8192 CLK
128 CLK
256 CLK
512 CLK
16 CLK
32 CLK
64 CLK
channel (S/H) operation
clk
PER
XMEGA A
cycles for dual
192 CLK
12 CLK
24 CLK
48 CLK
96 CLK
1 CLK
3 CLK
6 CLK
323
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