ATxmega32A4U Atmel Corporation, ATxmega32A4U Datasheet - Page 57

• Manufacturer Part Number: ATxmega32A4U
• Manufacturer: Atmel Corporation

Specifications of ATxmega32A4U

• Flash (kbytes): 32 Kbytes
• Pin Count: 44
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 34
• Ext Interrupts: 34
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 7
• Twi (i2c): 2
• Uart: 5
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 12
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 2
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 4
• Eeprom (bytes): 1024
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 5
• Output Compare Channels: 16
• Input Capture Channels: 16
• Pwm Channels: 16
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

5.13
5.13.1
8331A–AVR–07/11
Register Description – DMA Controller
CTRL – DMA Control Register
• Bit 7 – ENABLE: DMA Enable
Setting this bit enables the DMA controller. If the DMA controller is enabled and this bit is written
to zero, the ENABLE bit is not cleared before the internal transfer buffer is empty, and the DMA
data transfer is aborted.
• Bit 6 – RESET: DMA Software Reset
Writing a one to RESET will be ignored as long as DMA is enabled (ENABLE = 1). This bit can
be set only when the DMA controller is disabled (ENABLE = 0).
• Bit 5:4 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always
write these bits to zero when this register is written.
• Bit 3:2 – DBUFMODE[1:0]: DMA Double Buffer Mode
These bits enable the double buffer on the different channels according to
Table 5-1.
• Bit 1:0 – PRIMODE[1:0]: DMA Channel Priority Mode
These bits determine the internal channel priority according to
Table 5-2.
Bit
+0x00
Read/Write
Initial Value
DBUFMODE[1:0]
PRIMODE[1:0]
00
01
10
11
00
01
10
11
ENABLE
R/W
DMA double buffer settings.
DMA channel priority settings.
7
0
RR0123
CH0RR123
CH01RR23
CH0123
Group Configuration
DISABLED
CH01
CH23
CH01CH23
Group Configuration
RESET
R/W
6
0
R
5
–
0
4
–
R
0
Description
Round robin
Channel0 > Round robin (channel 1, 2 and 3)
Channel0 > Channel1 > Round robin (channel 2 and 3)
Channel0 > Channel1 > Channel2 > Channel3
Description
No double buffer enabled
Double buffer enabled on channel0/1
Double buffer enabled on channel2/3
Double buffer enabled on channel0/1 and channel2/3
Atmel AVR XMEGA AU
R/W
DBUFMODE[1:0]
3
0
R/W
2
0
Table
5-2.
R/W
1
0
PRIMODE[1:0]
Table
R/W
5-1.
0
0
CTRL
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