ATxmega32A4U Atmel Corporation, ATxmega32A4U Datasheet - Page 218
ATxmega32A4U
Manufacturer Part Number
ATxmega32A4U
Description
Manufacturer
Atmel Corporation
Specifications of ATxmega32A4U
Flash (kbytes)
32 Kbytes
Pin Count
44
Max. Operating Frequency
32 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
34
Ext Interrupts
34
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
7
Twi (i2c)
2
Uart
5
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
12
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
2
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
AES/DES
Sram (kbytes)
4
Eeprom (bytes)
1024
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.6 to 3.6
Operating Voltage (vcc)
1.6 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
5
Output Compare Channels
16
Input Capture Channels
16
Pwm Channels
16
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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18.3.2
18.3.3
8331A–AVR–07/11
STATUS – Status Register
INTCTRL – Interrupt Control Register
• Bit 7:1 – Reserved
These bits are reserved and will always be read as zero. For compatibility with future devices,
always write these bits to zero when this register is written.
• Bit 0 – SYNCBUSY: Synchronization Busy Flag
This flag is set when the CNT, CTRL, PER, or COMP register is busy synchronizing between the
RTC clock and system clock domains. THis flag is automatically cleared when the synchronisa-
tion is complete
• Bit 7:4 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always
write these bits to zero when this register is written.
• Bit 3:2 – COMPINTLVL[1:0]: Compare Match Interrupt Enable
These bits enable the RTC compare match interrupt and select the interrupt level, as described
in
rupt will trigger when COMPIF in the INTFLAGS register is set.
• Bit 1:0 – OVFINTLVL[1:0]: Overflow Interrupt Enable
These bits enable the RTC overflow interrupt and select the interrupt level, as described in
”Interrupts and Programmable Multilevel Interrupt Controller” on page
will trigger when OVFIF in the INTFLAGS register is set.
Bit
+0x01
Read/Write
Initial Value
Bit
+0x02
Read/Write
Initial Value
”Interrupts and Programmable Multilevel Interrupt Controller” on page
7
–
R
0
7
–
R
0
R
6
–
0
6
–
R
0
R
5
–
0
R
5
–
0
R
4
–
0
R
4
–
0
R/W
R
Atmel AVR XMEGA AU
3
–
0
COMPINTLVL[1:0]
3
0
R/W
R
2
–
0
2
0
132. The enabled interrupt
R
R/W
1
–
0
1
OVFINTLVL[1:0]
0
132. The enabled inter-
SYNCBUSY
R/W
R
0
0
0
0
INTCTRL
STATUS
218
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