ATxmega32A4U Atmel Corporation, ATxmega32A4U Datasheet - Page 55

• Manufacturer Part Number: ATxmega32A4U
• Manufacturer: Atmel Corporation

Specifications of ATxmega32A4U

• Flash (kbytes): 32 Kbytes
• Pin Count: 44
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 34
• Ext Interrupts: 34
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 7
• Twi (i2c): 2
• Uart: 5
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 12
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 2
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 4
• Eeprom (bytes): 1024
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 5
• Output Compare Channels: 16
• Input Capture Channels: 16
• Pwm Channels: 16
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

5.5
5.6
5.7
8331A–AVR–07/11
Addressing
Priority Between Channels
Double Buffering
effect. For a list of all transfer triggers, refer to
page
By default, a trigger starts a block transfer operation. When the block transfer is complete, the
channel is automatically disabled. When enabled again, the channel will wait for the next block
transfer trigger. It is possible to select the trigger to start a burst transfer instead of a block trans-
fer. This is called a single-shot transfer, and for each trigger only one burst is transferred. When
repeat mode is enabled, the next block transfer does not require a transfer trigger. It will start as
soon as the previous block is done.
If the trigger source generates a transfer request during an ongoing transfer, this will be kept
pending, and the transfer can start when the ongoing one is done. Only one pending transfer
can be kept, and so if the trigger source generates more transfer requests when one is already
pending, these will be lost.
The source and destination address for a DMA transfer can either be static or automatically
incremented or decremented, with individual selections for source and destination. When
address increment or decrement is used, the default behaviour is to update the address after
each access. The original source and destination addresses are stored by the DMA controller,
and so the source and destination addresses can be individually configured to be reloaded at
the following points:
If several channels request a data transfer at the same time, a priority scheme is available to
determine which channel is allowed to transfer data. Application software can decide whether
one or more channels should have a fixed priority or if a round robin scheme should be used. A
round robin scheme means that the channel that last transferred data will have the lowest
priority.
To allow for continuous transfer, two channels can be interlinked so that the second takes over
the transfer when the first is finished, and vice versa. This leaves time for the application to pro-
cess the data transferred by the first channel, prepare fresh data buffers, and set up the channel
registers again while the second channel is working. This is referred to as double buffering or
chained transfers.
When double buffering is enabled for a channel pair, it is important that the two channels are
configured with the same repeat count. The block sizes need not be equal, but for most applica-
tions they should be, along with the rest of the channel’s operation mode settings.
Note that the double buffering channel pairs are limited to channels 0 and 1 as the first pair and
channels 2 and 3 as the second pair. However, it is possible to have one pair operate in double
buffered mode while the other is left unused or operating independently.
• End of each burst transfer
• End of each block transfer
• End of transaction
• Never reloaded
63.
”TRIGSRC – DMA Channel Trigger Source” on
Atmel AVR XMEGA AU
55