ATxmega32A4U Atmel Corporation, ATxmega32A4U Datasheet - Page 336

• Manufacturer Part Number: ATxmega32A4U
• Manufacturer: Atmel Corporation

Specifications of ATxmega32A4U

• Flash (kbytes): 32 Kbytes
• Pin Count: 44
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 34
• Ext Interrupts: 34
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 7
• Twi (i2c): 2
• Uart: 5
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 12
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 2
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 4
• Eeprom (bytes): 1024
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 5
• Output Compare Channels: 16
• Input Capture Channels: 16
• Pwm Channels: 16
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

27.7
27.7.1
8331A–AVR–07/11
SDRAM Configuration
Supported Commands
Figure 27-8. Multiplexed SRAM LPC connection using ALE1 and ALE2
Chip Select 3 on the EBI can be configured from SDRAM operation, and the EBI must be config-
ured for 3-Port or 4-Port interface. The SDRAM can be configured for 4-bit or 8-bit data bus, and
4-Port interface must be used for 8-bit data bus. The SDRAM interface signals from the EBI to
the SDRAM is listed in
Table 27-2.
The SDRAM commands that are supported by the EBI is listed in
Table 27-3.
Signal
CS
WE
RAS
CAS
DQM
CKE
CLK
BA[1:0]
A[12:0]
A[10]
D[7:0]
Command
NOP
ACTIVE
READ
WRITE
PRECHARGE
SDRAM Interface signals
Supported SDRAM commands
EBI
Description
Chip Select
Write Enable
Row Address Strobe
Column Address Strobe
Data Mask Signal/ Output Enable
Clock Enable
Clock
Bank Address
Address bus
Precharge
Data bus
Description
No Operation
Activate the selected bank and select the row.
Input the starting column address and begin the burst read operation.
Input the starting column address and begin the burst write operation.
Deactivate the open row of selected bank or all banks
Table 27-2 on page
A[19:16]
A[15:8]/
AD[7:0]
ALE1
ALE2
D
G
336.
Q
D
G
Atmel AVR XMEGA AU
Q
D[7:0]
A[7:0]
A[15:8]
A[19:16]
Table 27-3 on page
SRAM
336.
336