ATxmega32A4U Atmel Corporation, ATxmega32A4U Datasheet - Page 347

• Manufacturer Part Number: ATxmega32A4U
• Manufacturer: Atmel Corporation

Specifications of ATxmega32A4U

• Flash (kbytes): 32 Kbytes
• Pin Count: 44
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 34
• Ext Interrupts: 34
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 7
• Twi (i2c): 2
• Uart: 5
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 12
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 2
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 4
• Eeprom (bytes): 1024
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 5
• Output Compare Channels: 16
• Input Capture Channels: 16
• Pwm Channels: 16
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

27.10.6
8331A–AVR–07/11
SDRAMCTRLC – SDRAM Control Register C
Table 27-17. SDRAM Row to Precharge Delay settings
• Bit 7:6 – WRDLY[1:0]: SDRAM Write Recovery Delay
These bits select the Write Recovery time in number of Clk
on page
Table 27-18. SDRAM Write Recovery Delay settings
• Bit 5:3 – ESRDLY[2:0]: SDRAM Exit Self Refresh to Active Delay
This field defines the delay between CKE set high and an ACTIVE command in a number of
Clk
Table 27-19. SDRAM Exit Self Refresh Delay settings
Bit
+0x09
Read/Write
Initial Value
PER2
ESRDLY[2:0]
WRDLY[1:0]
RPDLY[2:0]
cycles, according to
346.
000
001
010
011
100
101
110
111
000
001
010
011
100
00
01
10
11
R/W
7
0
WRDLY[1:0]
R/W
6
0
Group Configuration
0CLK
1CLK
2CLK
3CLK
4CLK
5CLK
6CLK
7CLK
Group Configuration
0CLK
1CLK
2CLK
3CLK
Group Configuration
0CLK
1CLK
2CLK
3CLK
4CLK
Table 27-19 on page
R/W
5
0
ESRDLY[1:0]
R/W
4
0
Description
0 Clk
1 Clk
2 Clk
3 Clk
4 Clk
5 Clk
6 Clk
7 Clk
Description
0 Clk
1 Clk
2 Clk
3 Clk
Description
0 Clk
1 Clk
2 Clk
3 Clk
4 Clk
R/W
3
0
347.
PER2
PER2
PER2
PER2
PER2
PER2
PER2
PER2
PER2
PER2
PER2
PER2
PER2
PER2
PER2
PER2
PER2
Atmel AVR XMEGA AU
cycles delay
cycles delay
cycles delay
cycles delay
cycles delay
cycles delay
cycles delay
cycles delay
cycles delay
cycles delay
cycles delay
cycles delay
cycles delay
cycles delay
cycles delay
cycles delay
cycles delay
R/W
2
0
PER2
ROWCOLDLY[1:0]
cycles, according to
R/W
1
0
R/W
0
0
SDRAMCTRLC
Table 27-15
347