AT89C5132 Atmel Corporation, AT89C5132 Datasheet - Page 78

• Manufacturer Part Number: AT89C5132
• Manufacturer: Atmel Corporation

Specifications of AT89C5132

• Flash (kbytes): 64 Kbytes
• Max. Operating Frequency: 20 MHz
• Cpu: 8051-12C
• Max I/o Pins: 44
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 1
• Uart: 1
• Adc Channels: 2
• Adc Resolution (bits): 10
• Adc Speed (ksps): 22.7
• Sram (kbytes): 2.25
• Self Program Memory: API
• Operating Voltage (vcc): 2.7 to 3.6
• Timers: 2
• Isp: UART/USB
• Watchdog: Yes

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AT89C5132
Reset Value = 0000 0000b
Table 64. UEPINT Register
UEPINT (S:F8h Read-only) – USB Endpoint Interrupt Register
Reset Value = 0000 0000b
Table 65. UEPIEN Register
UEPIEN (S:C2h) – USB Endpoint Interrupt Enable Register
Number
Number
7 - 4
7 - 4
Bit
Bit
3
2
1
0
7
3
2
1
0
7
-
-
Mnemonic Description
Mnemonic Description
EP3RST
EP2RST
EP1RST
EP0RST
EP3INT
EP2INT
EP1INT
EP0INT
Bit
Bit
6
6
-
-
-
-
Reserved
The values read from these Bits are always 0. Do not set these Bits.
Endpoint 3 FIFO Reset
Set and clear to reset the endpoint 3 FIFO prior to any other operation, upon
hardware reset or when an USB bus reset has been received.
Endpoint 2 FIFO Reset
Set and clear to reset the endpoint 2 FIFO prior to any other operation, upon
hardware reset or when an USB bus reset has been received.
Endpoint 1 FIFO Reset
Set and clear to reset the endpoint 1 FIFO prior to any other operation, upon
hardware reset or when an USB bus reset has been received.
Endpoint 0 FIFO Reset
Set and clear to reset the endpoint 0 FIFO prior to any other operation, upon
hardware reset or when an USB bus reset has been received.
Reserved
The values read from these Bits are always 0. Do not set these Bits.
Endpoint 3 Interrupt Flag
Set by hardware when an interrupt is triggered in UEPSTAX and the endpoint 3
interrupt is enabled in UEPIEN.
Must be cleared by software.
Endpoint 2 Interrupt Flag
Set by hardware when an interrupt is triggered in UEPSTAX and the endpoint 2
interrupt is enabled in UEPIEN.
Must be cleared by software.
Endpoint 1 Interrupt Flag
Set by hardware when an interrupt is triggered in UEPSTAX and the endpoint 1
interrupt is enabled in UEPIEN.
Must be cleared by software.
Endpoint 0 Interrupt Flag
Set by hardware when an interrupt is triggered in UEPSTAX and the endpoint 0
interrupt is enabled in UEPIEN.
Must be cleared by software.
5
5
-
-
4
4
-
-
EP3INTE
EP3INT
3
3
EP2INTE
EP2INT
2
2
EP1INTE
EP1INT
1
1
4173E–USB–09/07
EP0INTE
EP0INT
0
0