AT89C5132 Atmel Corporation, AT89C5132 Datasheet - Page 123

• Manufacturer Part Number: AT89C5132
• Manufacturer: Atmel Corporation

Specifications of AT89C5132

• Flash (kbytes): 64 Kbytes
• Max. Operating Frequency: 20 MHz
• Cpu: 8051-12C
• Max I/o Pins: 44
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 1
• Uart: 1
• Adc Channels: 2
• Adc Resolution (bits): 10
• Adc Speed (ksps): 22.7
• Sram (kbytes): 2.25
• Self Program Memory: API
• Operating Voltage (vcc): 2.7 to 3.6
• Timers: 2
• Isp: UART/USB
• Watchdog: Yes

Figure 19-5. Data Transmission Format (CPHA = 0)
Figure 19-6. Data Transmission Format (CPHA = 1)
19.1.5
4173E–USB–09/07
SS Management
MOSI (from Master)
MOSI (from Master)
SCK Cycle Number
SCK Cycle Number
MISO (from Slave)
MISO (from Slave)
to Capture Point
SCK (CPOL = 0)
SCK (CPOL = 1)
SCK (CPOL = 0)
SCK (CPOL = 1)
SPEN (Internal)
SPEN (Internal)
Capture Point
SS (to Slave)
SS (to Slave)
AT89C5132 captures data from the SI line while the selected slave captures data from the SO
line.
For simplicity, the following figures depict the SPI waveforms in idealized form and do not pro-
vide precise timing information. For timing parameters refer to the Section “AC Characteristics”.
Note:
Figure 19-5 shows an SPI transmission with CPHA = 0, where the first SCK edge is the MSB
capture point. Therefore the slave starts to output its MSB as soon as it is selected: SS asserted
to low level. SS must then be deasserted between each byte transmission (see Figure 19-7).
SPDAT must be loaded with data before SS is asserted again.
1. When the peripheral is disabled (SPEN = 0), default SCK line is high level.
MSB
MSB
MSB
MSB
1
1
bit 6
bit 6
bit 6
bit 6
2
2
bit 5
bit 5
bit 5
bit 5
3
3
bit 4
bit 4
bit 4
bit 4
4
4
bit 3
bit 3
bit 3
bit 3
5
5
bit 2
bit 2
bit 2
bit 2
6
6
bit 1
bit 1
bit 1
bit 1
7
7
LSB
LSB
LSB
8
8
LSB
AT89C5132
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