AT89C5132 Atmel Corporation, AT89C5132 Datasheet - Page 57

• Manufacturer Part Number: AT89C5132
• Manufacturer: Atmel Corporation

Specifications of AT89C5132

• Flash (kbytes): 64 Kbytes
• Max. Operating Frequency: 20 MHz
• Cpu: 8051-12C
• Max I/o Pins: 44
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 1
• Uart: 1
• Adc Channels: 2
• Adc Resolution (bits): 10
• Adc Speed (ksps): 22.7
• Sram (kbytes): 2.25
• Self Program Memory: API
• Operating Voltage (vcc): 2.7 to 3.6
• Timers: 2
• Isp: UART/USB
• Watchdog: Yes

13. Watchdog Timer
13.1
13.2
4173E–USB–09/07
Description
Watchdog Clock Controller
The AT89C5132 implement a hardware Watchdog Timer (WDT) that automatically resets the
chip if it is allowed to time out. The WDT provides a means of recovering from routines that do
not complete successfully due to software or hardware malfunctions.
The WDT consists of a 14-bit prescaler followed by a 7-bit programmable counter. As shown in
Figure 13-1, the 14-bit prescaler is fed by the WDT clock detailed in section "Watchdog Clock
Controller", page 57.
The Watchdog Timer Reset register (WDTRST, see Table 47) provides control access to the
WDT, while the Watchdog Timer Program register (WDTPRG, see Figure 48) provides time-out
period programming.
Three operations control the WDT:
•
•
•
Figure 13-1. WDT Block Diagram
As shown in Figure 13-2 the WDT clock (F
or the oscillator clock (F
issued from the Clock Controller block as detailed in section "Clock Controller", page 12. When
WTX2 bit is set, the WDT clock frequency is fixed and equal to the oscillator clock frequency
divided by 2. When cleared, the WDT clock frequency is equal to the oscillator clock frequency
divided by 2 in standard mode or to the oscillator clock frequency in X2 mode.
Figure 13-2. WDT Clock Controller and Symbol
Chip reset clears and disables the WDT.
Programming the time-out value to the WDTPRG register.
Writing a specific two-byte sequence to the WDTRST register clears and enables the WDT.
System
CLOCK
Reset
WDT
CLOCK
CLOCK
PER
OSC
RST
÷ 6
1Eh-E1h Decoder
÷
OSC
2
WDTRST
) depending on the WTX2 bit in CKCON register. These clocks are
CKCON.6
WTX2
0
1
RST
MATCH
14-bit Prescaler
EN
WDT
) is derived from either the peripheral clock (F
WDT Clock
CLOCK
OSC
RST
7-bit Counter
WDTPRG.2:0
WTO2:0
SET
Pulse Generator
AT89C5132
WDT Clock Symbol
OV
CLOCK
WDT
To internal
reset
RST
PER
57
)