AT89C5132 Atmel Corporation, AT89C5132 Datasheet - Page 133

• Manufacturer Part Number: AT89C5132
• Manufacturer: Atmel Corporation

Specifications of AT89C5132

• Flash (kbytes): 64 Kbytes
• Max. Operating Frequency: 20 MHz
• Cpu: 8051-12C
• Max I/o Pins: 44
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 1
• Uart: 1
• Adc Channels: 2
• Adc Resolution (bits): 10
• Adc Speed (ksps): 22.7
• Sram (kbytes): 2.25
• Self Program Memory: API
• Operating Voltage (vcc): 2.7 to 3.6
• Timers: 2
• Isp: UART/USB
• Watchdog: Yes

20.1.2
20.1.3
4173E–USB–09/07
Master Transmitter Mode
Master Receiver Mode
Table 19. Serial Clock Rates
Note:
In the master transmitter mode, a number of data Bytes are transmitted to a slave receiver (see
Figure 20-3). Before the master transmitter mode can be entered, SSCON must be initialized as
follows:
SSCR2:0 define the serial bit rate (see Table 19). SSPE must be set to enable the controller.
SSSTA, SSSTO and SSI must be cleared.
The master transmitter mode may now be entered by setting the SSSTA bit. The TWI logic will
now monitor the TWI bus and generate a START condition as soon as the bus becomes free.
When a START condition is transmitted, the serial interrupt flag (SSI bit in SSCON) is set, and
the status code in SSSTA is 08h. This status must be used to vector to an interrupt routine that
loads SSDAT with the slave address and the data direction bit (SLA+W). The serial interrupt flag
(SSI) must then be cleared before the serial transfer can continue.
When the slave address and the direction bit have been transmitted and an acknowledgment bit
has been received, SSI is set again and a number of status code in SSSTA are possible. There
are 18h, 20h or 38h for the master mode and also 68h, 78h or B0h if the slave mode was
enabled (SSAA = logic 1). The appropriate action to be taken for each of these status code is
detailed in Table 20. This scheme is repeated until a STOP condition is transmitted.
SSPE and SSCR2:0 are not affected by the serial transfer and are not referred to in Table 20.
After a repeated START condition (state 10h) the controller may switch to the master receiver
mode by loading SSDAT with SLA+R.
In the master receiver mode, a number of data Bytes are received from a slave transmitter (see
Figure 20-4). The transfer is initialized as in the master transmitter mode. When the START con-
dition has been transmitted, the interrupt routine must load SSDAT with the 7 - bit slave address
and the data direction bit (SLA+R). The serial interrupt flag (SSI) must then be cleared before
the serial transfer can continue.
2
0
0
0
0
1
1
1
1
Bit Rate
SSCR2
SSCRx
1
0
0
1
1
0
0
1
1
1. These bit rates are outside of the low speed standard specification limited to 100 kHz but can
0
0
1
0
1
0
1
0
1
be used with high speed TWI components limited to 400 kHz.
SSPE
0.5 < ⋅ < 125
F
PER
1
200
53.5
62.5
12.5
100
= 6 MHz
47
75
(1)
(1)
SSSTA
0
Bit Frequency (kHz)
0.67 < ⋅ < 166.7
F
PER
133.3
266.7
62.5
71.5
16.5
100
= 8 MHz
83
SSSTO
(1)
(1)
0
(1)
0.81 < ⋅ < 208.3
F
PER
SSI
104.2
166.7
333.3
78.125
125
20.83
0
= 10 MHz
89.3
(1)
(1)
(1)
(1)
(1)
SSAA
X
96 ⋅ (256 – reload value Timer 1)
F
AT89C5132
PER
Bit Rate
SSCR1
Divided By
128
480
112
96
80
60
30
Bit Rate
SSCR0
133