AT32UC3B1128 Atmel Corporation, AT32UC3B1128 Datasheet - Page 91

• Manufacturer Part Number: AT32UC3B1128
• Manufacturer: Atmel Corporation

Specifications of AT32UC3B1128

• Flash (kbytes): 128 Kbytes
• Pin Count: 48
• Max. Operating Frequency: 60 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 28
• Ext Interrupts: 28
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 3
• Twi (i2c): 1
• Uart: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 6
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0-3.6 or (1.65-1.95+3.0-3.6)
• Operating Voltage (vcc): 3.0-3.6 or (1.65-1.95+3.0-3.6)
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 10
• Output Compare Channels: 16
• Input Capture Channels: 6
• Pwm Channels: 13
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

9.2.1.2
9.2.2
32002F–03/2010
Monitor Mode
A typical debug session flow
Debug Mode is exited by the retd instruction, both in Monitor Mode and OCD Mode. This
restores PC from RAR_DBG and SR from RSR_DBG.
Figure 9-2 shows an example of a typical flow in Debug Mode. A software or hardware break-
point aborts the execution of an instruction and causes Debug Mode to be entered. If the Monitor
Mode (MM) bit in the Development Control (DC) OCD register is set, Monitor Mode is entered,
and the CPU jumps to the software debug monitor starting at EVBA+0x01C. Otherwise, OCD
Mode is entered, and the CPU stalls while waiting for instructions to be entered by the external
debugger through the Debug Instruction (DINST) OCD register. In either case, the D bit in the
CPU Status Register is set during the whole debug session, giving access to all privileged oper-
ations. Any number of instructions can be executed before returning to the breakpointed
instruction by the retd instruction. RAR_DBG stores the address of the breakpointed instruction,
and manipulating RAR_DBG in Debug Mode is useful if a different return address is desired (for
instance, to avoid repeated hits on a breakpoint instruction).
Figure 9-2.
If the Monitor Mode (MM) bit in the Development Control register (DC) is set, the CPU will enter
Debug Mode in Monitor Mode. Instructions are fetched from the monitor code located in the pro-
gram memory at the Exception Vector Base Address (EVBA) + 0x01C. The monitor code
contains the necessary mechanisms to read and modify CPU and system registers, and memory
Write Register commands
Debugger
External
DINST
Example of flow in Debug Mode.
Inst
external debugger
Instructions from
0 = OCD Mode
SR:D = 1
retd
DC:MM?
1 = Monitor Mode
Debug Mode
EV BA +0x300
Software debug monitor
Breakpointed instruction
User code
SR:D = 1
retd
LR_DBG
AVR32
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