AT32UC3B1128 Atmel Corporation, AT32UC3B1128 Datasheet - Page 78

• Manufacturer Part Number: AT32UC3B1128
• Manufacturer: Atmel Corporation

Specifications of AT32UC3B1128

• Flash (kbytes): 128 Kbytes
• Pin Count: 48
• Max. Operating Frequency: 60 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 28
• Ext Interrupts: 28
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 3
• Twi (i2c): 1
• Uart: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 6
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0-3.6 or (1.65-1.95+3.0-3.6)
• Operating Voltage (vcc): 3.0-3.6 or (1.65-1.95+3.0-3.6)
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 10
• Output Compare Channels: 16
• Input Capture Channels: 6
• Pwm Channels: 13
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

32002F–03/2010
The stcond instruction takes 2 cycles if the store is not performed, 3 cycles if the store is
performed.
All issue latencies are given for accesses to IRAM or LOCAL. These timings must be modified
as follows for accesses to BOOT or HSB sections:
Table 8-7.
Mnemonics
ld.ub
ld.ub{cond4}
ld.sb
ld.sb{cond4}
• A byte, halfword or word load requires 1+w cycles in addition to the count listed in
• A doubleword load performs two memory accesses, so 2(1+w) cycles are needed in addition
• A byte, halfword or word store requires (1+w) cycles in addition to the count listed in
• A doubleword store performs two memory accesses, but these will be pipelined. The last of
where w is the number of wait states from the slave and bus system. The pipeline will stall
during these cycles.
to the count listed in
7, where w is the number of wait states from the slave and bus system. Stores to BOOT or
HSB can be performed in the background, so the pipeline will only stall if another memory
access is attempted during these w cycles. However, multiple stores to addresses in BOOT
or HSB can be automatically combined by the memory interface to create bursts on the HSB
bus. This means that any consecutive stores to BOOT or HSB sections will not stall the
pipeline unless the bus itself inserts wait cycles, for example due to wait states or bus
contention. Instructions not performing memory accesses will never stall the pipeline when
executed after stores to BOOT or HSB.
these accesses will stall if the instruction following the doubleword is a memory access
instruction other than a store to BOOT or HSB. Therefore, a non-memory instruction or
another store to BOOT or HSB should be scheduled after a doubleword store to BOOT or
HSB for maximum performance.
Load and store instructions
C
C
C
E
E
E
E
E
E
Operands
Rd, Rp++
Rd, --Rp
Rd, Rp[disp]
Rd, Rp[disp]
Rd, Rb[Ri<<sa]
Rd, Rp[disp]
Rd, Rp[disp]
Rd, Rb[Ri<<sa]
Rd, Rp[disp]
Table
8-7. The pipeline will stall during these cycles.
Description
Load unsigned byte with post-increment.
Load unsigned byte with pre-decrement.
Load unsigned byte with displacement.
Indexed Load unsigned byte.
Load unsigned byte with displacement if
condition satisfied. CPU revision 2 and higher
only.
Load signed byte with displacement.
Indexed Load signed byte.
Load signed byte with displacement if condition
satisfied. CPU revision 2 and higher only.
AVR32
Table
2
2
Issue
latency
IRAM
1
1
1
1
1
1
1
Table 8-
8-7,
78