AT32UC3B1128 Atmel Corporation, AT32UC3B1128 Datasheet - Page 17

• Manufacturer Part Number: AT32UC3B1128
• Manufacturer: Atmel Corporation

Specifications of AT32UC3B1128

• Flash (kbytes): 128 Kbytes
• Pin Count: 48
• Max. Operating Frequency: 60 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 28
• Ext Interrupts: 28
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 3
• Twi (i2c): 1
• Uart: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 6
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0-3.6 or (1.65-1.95+3.0-3.6)
• Operating Voltage (vcc): 3.0-3.6 or (1.65-1.95+3.0-3.6)
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 10
• Output Compare Channels: 16
• Input Capture Channels: 6
• Pwm Channels: 13
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

2.6
2.7
32002F–03/2010
MSU_ADDRHI, MSU_ADDRLO, MSU_LENGTH, MSU_CTRL, MSU_STATUS, MSU_DATA, MSU_TAIL -
COMPARE and COUNT registers
Configuration Registers
Memory Service Unit Registers
These registers are system register mappings of the Memory Service Unit Registers. Refer to
Section 9.8 ”Memory Service Unit” on page 138
The COUNT register increments once every clock cycle, regardless of pipeline stalls and
flushes. The COUNT register can both be read and written. The COUNT register can be used
together with the COMPARE register to create a timer with periodic interrupt. The COUNT regis-
ter is written to zero upon reset and compare match if the CPUCR[NOCOMPRES] bit is cleared,
otherwise COUNT is not reset on compare match. Incrementation of the COUNT register can
not be disabled. The COUNT register will increment even though a compare interrupt is pending.
The COMPARE register holds a value that the COUNT register is compared against. The COM-
PARE register can both be read and written. When the COMPARE and COUNT registers match,
a compare interrupt request is generated and COUNT is reset to 0. COUNT will thereafter con-
tinue incrementing in the following clock cycle. The interrupt request is routed out to the interrupt
controller, which may forward the request back to the processor as a normal interrupt request at
a priority level determined by the interrupt controller. Writing a value to the COMPARE register
clears any pending compare interrupt requests. The compare and exception generation feature
is disabled if the COMPARE register contains the value zero. The COMPARE register is written
to zero upon reset.
COUNT and COMPARE are clocked by a dedicated clock with the same frequency as the CPU
clock. This allows them to operate in some of the sleep modes. They can therefore be used as
timers even when the system use sleep modes. Consult the clock system documentation for
information on which sleep modes COUNT and COMPARE are operational.
Configuration registers are used to inform applications and operating systems about the setup
and configuration of the processor on which it is running, see
AVR32UC implements the following read-only configuration registers.
Figure 2-4.
CONFIG0
CONFIG1
31
31
IMMU SZ
Processor ID
Configuration Registers
26
25
24
DMMU SZ
23
-
20
20 19
19
Processor
Revision
ISET
16 15
16
for details.
15
ILSZ
AT
13 12
13
12
IASS
AR
Figure 2-4 on page
10
10 9
9
MMUT
DSET
7 6
F
6 5
5
J
DLSZ
17.
4
P O
AVR32
3 2
3
S
2
DASS
D R
1
0
0
17