AT32UC3B1128 Atmel Corporation, AT32UC3B1128 Datasheet - Page 6

• Manufacturer Part Number: AT32UC3B1128
• Manufacturer: Atmel Corporation

Specifications of AT32UC3B1128

• Flash (kbytes): 128 Kbytes
• Pin Count: 48
• Max. Operating Frequency: 60 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 28
• Ext Interrupts: 28
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 3
• Twi (i2c): 1
• Uart: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 6
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0-3.6 or (1.65-1.95+3.0-3.6)
• Operating Voltage (vcc): 3.0-3.6 or (1.65-1.95+3.0-3.6)
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 10
• Output Compare Channels: 16
• Input Capture Channels: 6
• Pwm Channels: 13
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

32002F–03/2010
Revision 3 of the AVR32UC CPU added the following system registers:
Revision 3 of the AVR32UC CPU added the following bit in the status register:
AVR32UC CPU revision 2 is fully backward-compatible with revision 1, ie. code compiled for
revision 1 is binary-compatible with revision 2 CPUs.
AVR32UC CPU revision 3 is fully backward-compatible with revision 1 and 2, ie. code compiled
for revision 1 and 2 is binary-compatible with revision 3 CPUs.
The Architecture Revision field in the CONFIG0 system register identifies which architecture
revision is implemented in a specific device. The “Processor and Architecture”-chapter of the
device datasheet identifies the CPU revision used.
• sscall
• retss
• Floating-point instructions as described in
• SS_STATUS
• SS_ADRF, SS_ADRR, SS_ADR0, SS_ADR1
• SS_SP_SYS, SS_SP_APP
• SS_RAR, SS_RSR
• SS
Section 4. on page
40.
AVR32
6