AT32UC3B1128 Atmel Corporation, AT32UC3B1128 Datasheet - Page 115

• Manufacturer Part Number: AT32UC3B1128
• Manufacturer: Atmel Corporation

Specifications of AT32UC3B1128

• Flash (kbytes): 128 Kbytes
• Pin Count: 48
• Max. Operating Frequency: 60 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 28
• Ext Interrupts: 28
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 3
• Twi (i2c): 1
• Uart: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 6
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0-3.6 or (1.65-1.95+3.0-3.6)
• Operating Voltage (vcc): 3.0-3.6 or (1.65-1.95+3.0-3.6)
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 10
• Output Compare Channels: 16
• Input Capture Channels: 6
• Pwm Channels: 13
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

9.3.3.6
9.3.3.7
32002F–03/2010
Transmit queue and overruns
Trace and reset
Figure 9-5.
Messages from various sources are inserted in a Transmit Queue (TXQ), which stores a number
of frames. This queue acts as a FIFO which allows messages to be inserted more rapidly than
they can be retrieved by the emulator.
The queue holds 16 frames. If more messages are inserted than there is room for in the queue,
information will be lost, and an overrun situation occurs. The TXQ will block any more messages
from being inserted, and allow the queue to be emptied by the emulator before allowing any
more messages to be inserted. The first message to be inserted after the overrun is cleared, is
an Error message, which informs the emulator that an overrun has occurred and which types of
trace messages have been lost. After this, transmission continues as normal.
Alternatively, the user can configure the OCD to halt the CPU to prevent overruns. This can be
done selectively for different message types, and is controlled by writing to the Overrun Control
(OVC) bits in the DC register.
If any of the OVC bits are set, watchpoint trace messages will usually not generate TXQ over-
flow. However, triggering an program and data watchpoint on the same instruction may in some
rare cases cause an overrun independently of the OVC settings, since a large amount of trace
message data will be produced for this instruction.
All pending trace messages in the Transmit Queue are flushed if: the OCD is reset by a system
reset; the OCD is disabled; or an application reset is triggered by writing to the DC:RES bit.
Thus, if the CPU is reset, but not the OCD, the program flow can be observed by program trace.
However, if the debugger resets the system, the remaining messages in the queue are of no
value, and expected to be flushed.
Note that if the OCD is disabled (by clearing DC:DBE or by a system reset), trace is suspended
until DC:DBE is written to one. The DC:TM bits must be written simultaneously, and define which
trace features should now be active.
Similarly, when an application reset is triggered by writing DC:RES, the DC:TM bits are written
simultaneously and define which trace features should now be active.
M C K O ( D D R = 1 )
M C K O ( D D R = 0 )
M S E O [1 . . 0 ]
M D O [ 5. . 0 ]
Example of a Nexus message transmission with single and double datarate.
IDLE
1 1
TCODE = 4
0 0 0 1 0 0
SOM
0 0
NORMAL
1 1 1 1 1 0
EVT-ID = 2
Zero stuffing
0 0 0 0 1 1
EVLP
0 1
I-CNT = 63
0 0 0 1 0 1
U-ADDR = 5
EOM
1 1
AVR32
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