AT32UC3B1128 Atmel Corporation, AT32UC3B1128 Datasheet - Page 26

• Manufacturer Part Number: AT32UC3B1128
• Manufacturer: Atmel Corporation

Specifications of AT32UC3B1128

• Flash (kbytes): 128 Kbytes
• Pin Count: 48
• Max. Operating Frequency: 60 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 28
• Ext Interrupts: 28
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 3
• Twi (i2c): 1
• Uart: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 6
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0-3.6 or (1.65-1.95+3.0-3.6)
• Operating Voltage (vcc): 3.0-3.6 or (1.65-1.95+3.0-3.6)
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 10
• Output Compare Channels: 16
• Input Capture Channels: 6
• Pwm Channels: 13
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

3.9
32002F–03/2010
Entry points for events
Many peripheral modules that are able to assert interrupt requests have control registers or
other means of masking one or more of its interrupt requests. For example, a USART can con-
tain an interrupt mask register with individual bits for masking “TX ready” and “RX ready”
interrupts. Writing to such a mask register may cause a pending interrupt request from that mod-
ule to be disasserted.
The programmer must at all times make sure that an action that will disassert interrupts at the
interrupt source is not performed if it is possible that the interrupt sequencing hardware is in the
processing of handling the interrupt request that will be disasserted by the action. It is safe to
perform such an action if one of the following is true:
Code 3-3.
If the interrupt request is disasserted during the critical clock cycles where the sequencing hard-
ware is active handling this interrupt request, the CPU may enter an UNPREDICTABLE state.
Several different event handler entry points exists. In AVR32UC, the reset address is
0x8000_0000. This places the reset address in the boot flash memory area.
TLB miss exceptions and scall have a dedicated space relative to EVBA where their event han-
dler can be placed. This speeds up execution by removing the need for a jump instruction placed
at the program address jumped to by the event hardware. All other exceptions have a dedicated
event routine entry point located relative to EVBA. The handler routine address identifies the
exception source directly.
AVR32UC uses the ITLB and DTLB protection exceptions to signal a MPU protection violation.
ITLB and DTLB miss exceptions are used to signal that an access address did not map to any of
the entries in the MPU. TLB multiple hit exception indicates that an access address did map to
multiple TLB entries, signalling an error.
All external interrupt requests have entry points located at an offset relative to EVBA. This
autovector offset is specified by an external Interrupt Controller. The programmer must make
sure that none of the autovector offsets interfere with the placement of other code. The autovec-
tor offset has 14 address bits, giving an offset of maximum 16384 bytes.
Special considerations should be made when loading EVBA with a pointer. Due to security con-
siderations, the event handlers should be located in non-writeable flash memory, or optionally in
a privileged memory protection region if an MPU is present.
• The SREG GM or IxM bit corresponding to the priority of the interrupt request to be masked
• It can be guaranteed that the interrupt request being masked by the action is disasserted
is set before the action is performed.
when the action is initiated and being performed.
// Masking TX_READY IRQ in a peripheral by setting the TXMASK bit in the
// IRQMASK register of the peripheral.
// Could alternatively mask the SREG IxM bit associated with the IRQ source
disassert_periph_tx_irq:
ssrf AVR32_SREG_GM
mems PERIPH_IRQMASK, PERIPH_TXMASK
csrf AVR32_SREG_GM
Masking IRQs in a peripheral module which may assert an IRQ at any time
AVR32
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