AT32UC3B1128 Atmel Corporation, AT32UC3B1128 Datasheet
AT32UC3B1128
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AT32UC3B1128 Summary of contents
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... Sample Rate KHz ® • QTouch Library Support – Capacitive Touch Buttons, Sliders, and Wheels – QTouch and QMatrix Acquisition ® ® AVR Microcontroller 2 C-compatible 32-bit ATMEL AVR Microcontroller AT32UC3B0512 AT32UC3B0256 AT32UC3B0128 AT32UC3B064 AT32UC3B1512 AT32UC3B1256 AT32UC3B1128 AT32UC3B164 32059L–01/2012 ...
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On-Chip Debug System (JTAG interface) – Nexus Class 2+, Runtime Control, Non-Intrusive Data and Program Trace • 64-pin TQFP/QFN (44 GPIO pins), 48-pin TQFP/QFN (28 GPIO pins) • 5V Input Tolerant I/Os, including 4 high-drive pins • Single 3.3V ...
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Description The AT32UC3B is a complete System-On-Chip microcontroller based on the AVR32 UC RISC processor running at frequencies MHz. AVR32 high-performance 32-bit RISC microprocessor core, designed for cost-sensitive embedded applications, with particular empha- ...
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Overview 2.1 Blockdiagram Figure 2-1. Block diagram TCK TDO INTERFACE TDI TMS MCKO MDO[5..0] MSEO[1..0] EVTI_N EVTO_N VBUS D+ D- INTERFACE ID VBOF PA PB EXTINT[7..0] KPS[7..0] NMI 115 kHz RCOSC 32 KHz XIN32 XOUT32 OSC XIN0 OSC0 XOUT0 ...
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Configuration Summary The table below lists all AT32UC3B memory and package configurations: Table 3-1. Feature Flash SRAM GPIO External Interrupts TWI USART Peripheral DMA Channels SPI Full Speed USB SSC Audio Bitstream DAC Timer/Counter Channels PWM Channels Watchdog Timer ...
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Package and Pinout 4.1 Package The device pins are multiplexed with peripheral functions as described in the Peripheral Multi- plexing on I/O Line section. Figure 4-1. VDDPLL VDDCORE RESET_N 32059L–AVR32–01/2012 TQFP64 / QFN64 Pinout GND ...
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Figure 4-2. Note: 4.2 Peripheral Multiplexing on I/O lines 4.2.1 Multiplexed signals Each GPIO line can be assigned to one of 4 peripheral functions only avail- able for UC3Bx512 parts). The following table ...
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Table 4-1. GPIO Controller Function Multiplexing 10 12 PA06 GPIO PA07 GPIO PA08 GPIO PA09 GPIO PA10 GPIO PA11 GPIO PA12 GPIO ...
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Table 4-1. GPIO Controller Function Multiplexing 55 PB09 GPIO 41 57 PB10 GPIO 42 58 PB11 GPIO 43 4.2.2 JTAG Port Connections If the JTAG is enabled, the JTAG will take control over a number of pins, irrespective of the ...
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Table 4-4. QFP48 pin 4.3 High Drive Current GPIO Ones of GPIOs can be used to drive twice current than other GPIO capability (see Electrical Characteristics section). Table 4-5. 5. Signals Description The following table gives details on the signal ...
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Table 5-1. Signal Description List (Continued) Signal Name Function VDDOUT Voltage Regulator Output GNDANA Analog Ground GND Ground XIN0, XIN1, XIN32 Crystal Input XOUT0, XOUT1, Crystal Output XOUT32 TCK Test Clock TDI Test Data ...
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Table 5-1. Signal Description List (Continued) Signal Name Function MISO Master In Slave Out MOSI Master Out Slave In NPCS0 - NPCS3 SPI Peripheral Chip Select SCK Clock RX_CLOCK SSC Receive Clock RX_DATA SSC Receive Data RX_FRAME_SYNC SSC Receive Frame ...
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Table 5-1. Signal Description List (Continued) Signal Name Function DCD Data Carrier Detect DSR Data Set Ready DTR Data Terminal Ready RI Ring Indicator RTS Request To Send RXD Receive Data TXD Transmit Data AD0 - AD7 Analog input pins ...
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RESET_N pin The RESET_N pin is a schmitt input and integrates a permanent pull-up resistor to VDDIO. As the product integrates a power-on reset cell, the RESET_N pin can be left unconnected in case no reset from the system ...
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Figure 5-1. 3.3V 5.6.2 Voltage Regulator 5.6.2.1 Single Power Supply The AT32UC3B embeds a voltage regulator that converts from 3.3V to 1.8V. The regulator takes its input voltage from VDDIN, and supplies the output voltage on VDDOUT that should be ...
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Refer to characteristics. For decoupling recommendations for VDDIO, VDDANA, VDDCORE and VDDPLL, please refer to the Schematic checklist. 5.6.2.2 Dual Power Supply In case of dual power supply, VDDIN and VDDOUT should be connected to ground to prevent from leakage ...
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Processor and Architecture Rev: 1.0.0.0 This chapter gives an overview of the AVR32UC CPU. AVR32UC is an implementation of the AVR32 architecture. A summary of the programming model, instruction set, and MPU is pre- sented. For further details, see ...
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The register file is organized as sixteen 32-bit registers and includes the Program Counter, the Link Register, and the Stack Pointer. In addition, register R12 is designed to hold return values from function calls and is used implicitly by some ...
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Figure 6-1. 6.3.1 Pipeline Overview AVR32UC has three pipeline stages, Instruction Fetch (IF), Instruction Decode (ID), and Instruc- tion Execute (EX). The EX stage is split into three parallel subsections, one arithmetic/logic (ALU) section, one multiply (MUL) section, and one ...
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Figure 6-2. 6.3.2 AVR32A Microarchitecture Compliance AVR32UC implements an AVR32A microarchitecture. The AVR32A microarchitecture is tar- geted at cost-sensitive, lower-end applications like smaller microcontrollers. This microarchitecture does not provide dedicated hardware registers for shadowing of register file registers in interrupt ...
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The following table shows the instructions with support for unaligned addresses. All other instructions require aligned addresses. Table 6-1. Instruction ld.d st.d 6.3.6 Unimplemented Instructions The following instructions are unimplemented in AVR32UC, and will cause an Unimplemented Instruction Exception if ...
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Programming Model 6.4.1 Register File Configuration The AVR32UC register file is shown below. Figure 6-3. Application Bit 31 Bit SP_APP R12 R11 R10 R9 R8 INT0PC R7 INT1PC R6 FINTPC R5 SMPC ...
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Figure 6-5. Bit 6.4.3 Processor States 6.4.3.1 Normal RISC State The AVR32 processor supports several different execution contexts as shown in page 23. Table 6-2. Priority N/A N/A Mode ...
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All interrupt levels are by default disabled when debug state is entered, but they can individually be switched on by the monitor routine by clearing the respective mask bit in the status register. Debug state can be entered as described ...
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Table 6-3. Reg # 33- ...
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Table 6-3. Reg # 100 101 102 103-191 192-255 6.5 Exceptions and Interrupts AVR32UC incorporates a powerful exception handling scheme. The different exception sources, like Illegal Op-code and external interrupt requests, have ...
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The user must also make sure that the system stack is large enough so that any event is able to push the required registers to stack. If the system stack is full, and an event occurs, the system will enter ...
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Upon entry into Debug mode, hardware sets the SR[D] bit and jumps to the Debug Exception handler. By default, Debug mode executes in the exception context, but with dedicated Return Address Register and Return Status Register. These dedicated ...
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Table 6-4. Priority and Handler Addresses for Events Priority Handler Address 1 0x8000_0000 2 Provided by OCD system 3 EVBA+0x00 4 EVBA+0x04 5 EVBA+0x08 6 EVBA+0x0C 7 EVBA+0x10 8 Autovectored 9 Autovectored 10 Autovectored 11 Autovectored 12 EVBA+0x14 13 EVBA+0x50 ...
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Module Configuration All AT32UC3B parts do not implement the same CPU and Architecture Revision. Table 6-5. Part Name AT32UC3Bx512 AT32UC3Bx256 AT32UC3Bx128 AT32UC3Bx64 32059L–AVR32–01/2012 CPU and Architecture Revision Architecture Revision ...
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... KBytes (AT32UC3B064, AT32UC3B164) • Internal High-Speed SRAM, Single-cycle access at full speed – 96KBytes ((AT32UC3B0512, AT32UC3B1512) – 32KBytes (AT32UC3B0256, AT32UC3B0128, AT32UC3B1256 and AT32UC3B1128) – 16KBytes (AT32UC3B064 and AT32UC3B164) 7.2 Physical Memory Map The system bus is implemented as a bus matrix. All system bus addresses are fixed, and they are never remapped in any way, not even in boot ...
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Peripheral Address Map Table 7-2. Peripheral Address Mapping Address 0xFFFE0000 0xFFFE1000 0xFFFE1400 0xFFFF0000 0xFFFF0800 0xFFFF0C00 0xFFFF0D00 0xFFFF0D30 0xFFFF0D80 0xFFFF1000 0xFFFF1400 0xFFFF1800 0xFFFF1C00 0xFFFF2400 0xFFFF2C00 0xFFFF3000 0xFFFF3400 0xFFFF3800 32059L–AVR32–01/2012 Peripheral Name USB USB 2.0 Interface - USB HMATRIX HSB Matrix ...
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Table 7-2. Peripheral Address Mapping 0xFFFF3C00 0xFFFF4000 7.4 CPU Local Bus Mapping Some of the registers in the GPIO module are mapped onto the CPU local bus, in addition to being mapped on the Peripheral Bus. These registers can therefore ...
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Boot Sequence This chapter summarizes the boot sequence of the AT32UC3B. The behaviour after power-up is controlled by the Power Manager. For specific details, refer to section Power Manager (PM). 8.1 Starting of clocks After power-up, the device will ...
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Power Manager (PM) Rev: 2.3.0.2 9.1 Features • Controls integrated oscillators and PLLs • Generates clocks and resets for digital logic • Supports 2 crystal oscillators 0.4-20 MHz • Supports 2 PLLs 80-240 MHz • Supports 32 KHz ultra-low ...
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Block Diagram Figure 9-1. Voltage Regulator Calibration fuses Registers Brown-Out Detector Power-On Detector External Reset Pad 32059L–AVR32–01/2012 Power Manager block diagram RCOSC Oscillator 0 PLL0 PLL1 Oscillator 1 O SC/PLL Control signals Oscillator and PLL Control Sleep Controller Interrupts ...
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Product Dependencies 9.4.1 I/O Lines The PM provides a number of generic clock outputs, which can be connected to output pins, multiplexed with GPIO lines. The programmer must first program the GPIO controller to assign these pins to their ...
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The PM masks the oscillator outputs during the start-up time, to ensure that no unstable clocks propagate to the digital logic. The OSCnRDY bits in POSCSR are automatically set and cleared according to the status of the oscillators. A zero ...
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When the PLL is switched on, or when changing the clock source or multiplication factor for the PLL, the PLL is unlocked and the output frequency is undefined. The PLL clock for the digital logic is automatically masked when the ...
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The clock domains can be shut down in sleep mode, as ...
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Similarly, the clock for the PBA, and PBB can be divided by writing their respective bitfields. To ensure correct operation, frequencies must be selected so that f must never exceed the specified maximum frequency for each clock domain. CKSEL can ...
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Sleep modes In normal operation, all clock domains are active, allowing software execution and peripheral operation. When the CPU is idle possible to switch off the CPU clock and optionally other clock domains to save power. This ...
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The power level of the internal voltage regulator is also adjusted according to the sleep mode to reduce the internal regulator power consumption. 9.5.7.3 Precautions when entering sleep mode Modules communicating with external circuits should normally be disabled before entering ...
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Figure 9-5. Osc0 clock Osc1 clock PLL0 clock PLL1 clock 9.5.8.1 Enabling a generic clock A generic clock is enabled by writing the CEN bit in GCCTRL to 1. Each generic clock can use either Oscillator ...
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Generic clock implementation In AT32UC3B, there are 5 generic clocks. These are allocated to different functions as shown in Table 9-2. Table 9-2. Clock number 9.5.9 Divided PB clocks The clock generator in the Power Manager provides divided PBA ...
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Figure 9- r addition to the listed reset types, the JTAG can keep parts of the device statically reset through the JTAG Reset Register. See JTAG documentation ...
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Table 9-4 Table 9-4. Effect of the different reset events CPU/HSB/PBA/PBB (excluding Power Manager) 32 KHz oscillator RTC control register GPLP registers Watchdog control register Voltage Calibration register RC Oscillator Calibration register BOD control register Bandgap control register Clock control ...
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See Electrical Characteristics for parametric details. 9.5.11.3 External Reset The external reset detector monitors the state of the RESET_N pin. By default, a low level on this pin will generate a reset. 9.5.12 Calibration registers The Power Manager controls the ...
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User Interface Table 9-5. Offset 0x0000 Main Clock Control Register 0x0004 0x0008 0x000C 0x0010 0x0014 0x0020 0x0024 0x0028 Oscillator 0 Control Register 0x002C Oscillator 1 Control Register 0x0030 Oscillator 32 Control Register 0x0040 Interrupt Enable Register 0x0044 Interrupt Disable ...
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Main Clock Control Register Name: MCCTRL Access Type: Read/Write Offset: 0x000 Reset Value: 0x00000000 • OSC1EN: Oscillator 1 Enable 0: Oscillator 1 is ...
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Clock Select Register Name: CKSEL Access Type: Read/Write Offset: 0x004 Reset Value: 0x00000000 31 30 PBBDIV - 23 22 PBADIV - 15 14 HSBDIV - 7 6 CPUDIV - • PBBDIV, PBBSEL: PBB Division and Clock Select PBBDIV = ...
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Clock Mask Register Name: CPU/HSB/PBA/PBBMASK Access Type: Read/Write Offset: 0x008, 0x00C, 0x010, 0x014 Reset Value 32059L–AVR32–01/2012 MASK[31:24 MASK[23:16 MASK[15: ...
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MASK: Clock Mask If bit n is cleared, the clock for module n is stopped. If bit n is set, the clock for module n is enabled according to the current power mode. The number of implemented bits in ...
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PLL Control Register Name: PLL0,1 Access Type: Read/Write Offset: 0x020, 0x024 Reset Value: 0x00000000 • PLLCOUNT: PLL Count Specifies the number of slow ...
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Table 9-7. PLLOPT Fields Description in AT32UC3B Description PLLOPT[0]: VCO frequency 0 160MHz<f 1 80MHz<f PLLOPT[1]: Output divider PLLOPT[2] 0 Wide Bandwidth Mode enabled 1 Wide Bandwidth Mode disabled • • PLLOSC: PLL Oscillator Select ...
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Oscillator 0/1 Control Register Name: OSCCTRL0,1 Access Type: Read/Write Offset: 0x028, 0x02C Reset Value: 0x00000000 • STARTUP: Oscillator Startup Time Select startup time ...
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KHz Oscillator Control Register Name: OSCCTRL32 Access Type: Read/Write Offset: 0x030 Reset Value: 0x00010000 Note: This register is only reset by Power-On ...
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Interrupt Enable Register Name: IER Access Type: Write-only Offset: 0x040 Reset Value: 0x00000000 OSC0RDY MSKRDY Writing a zero to a bit in this register has ...
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Interrupt Disable Register Name: IDR Access Type: Write-only Offset: 0x044 Reset Value: 0x00000000 OSC0RDY MSKRDY Writing a zero to a bit in this register has ...
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Interrupt Mask Register Name: IMR Access Type: Read-only Offset: 0x048 Reset Value: 0x00000000 OSC0RDY MSKRDY 0: The corresponding interrupt is disabled. 1: The corresponding interrupt ...
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Interrupt Status Register Name: ISR Access Type: Read-only Offset: 0x04C Reset Value: 0x00000000 OSC0RDY MSKRDY • BODDET: Brown out detection Set to 1 when 0 ...
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Interrupt Clear Register Name: ICR Access Type: Write-only Offset: 0x050 Reset Value: 0x00000000 OSC0RDY MSKRDY Writing a zero to a bit in this register has ...
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Power and Oscillators Status Register Name: POSCSR Access Type: Read-only Offset: 0x054 Reset Value: 0x00000000 OSC0RDY MSKRDY • BODDET: Brown out detection 0: No BOD ...
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Generic Clock Control Register Name: GCCTRL Access Type: Read/Write Offset: 0x060 - 0x070 Reset Value: 0x00000000 There is one GCCTRL register per generic clock in ...
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RC Oscillator Calibration Register Name: RCCR Access Type: Read/Write Offset: 0x0C0 Reset Value • KEY: Register Write protection This field must be written twice, first with ...
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Bandgap Calibration Register Name: BGCR Access Type: Read/Write Offset: 0x0C4 Reset Value • KEY: Register Write protection This field must be written twice, first ...
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Voltage Regulator Calibration Register Name:: VREGCR Register access: Read/Write Offset: 0x0C8 Reset Value • KEY: Register Write protection • This field must be written ...
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BOD Level Register Name: BOD Access Type: Read/Write Offset: 0x0D0 Reset Value HYST • KEY: Register Write protection • This field must be written twice, ...
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Reset Cause Register Name: RCAUSE Access Type: Read-only Offset: 0x140 Reset Value: Latest Reset Source • OCDRST: OCD Reset • The CPU was ...
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Asynchronous Wake Up Enable Register Name: AWEN Access Type: Read/Write Offset: 0x144 Reset Value: 0x00000000 • • USB_WAKEN : USB Wake Up Enable ...
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General Purpose Low-power Register 0/1 Name: GPLP Access Type: Read/Write Offset: 0x200 Reset Value: 0x00000000 These registers are general purpose 32-bit registers that are reset only by power-on-reset. Any other reset ...
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Real Time Counter (RTC) Rev: 2.3.1.1 10.1 Features • 32-bit real-time counter with 16-bit prescaler • Clocked from RC oscillator or 32KHz oscillator • Long delays – Max timeout 272years • High resolution: Max count frequency 16KHz • Extremely ...
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Power Management The RTC remains operating in all sleep modes except Static mode. Interrupts are not available in DeepStop mode. 10.4.2 Clocks The RTC can use the system RC oscillator as clock source. This oscillator is always enabled whenever ...
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The RTC count value can be read from or written to the Value register (VAL). Due to synchroni- zation, continuous reading of the VAL register with the lowest prescaler setting will skip every other value. 10.5.1.3 RTC interrupt The RTC ...
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User Interface Table 10-1. RTC Register Memory Map Offset 0x00 Control Register 0x04 0x08 0x10 Interrupt Enable Register 0x14 Interrupt Disable Register 0x18 Interrupt Mask Register 0x1C Interrupt Status Register 0x20 Interrupt Clear Register 32059L–AVR32–01/2012 Register Register Name Value ...
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Control Register Name: CTRL Access Type: Read/Write Offset: 0x00 Reset Value: 0x00010000 • CLKEN: Clock Enable 1: The clock is enabled. 0: The ...
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Value Register Name: VAL Access Type: Read/Write Offset: 0x04 Reset Value: 0x00000000 • VAL[31:0]: RTC Value This value is incremented on every rising edge of the source clock. 32059L–AVR32–01/2012 29 28 ...
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Top Register Name: TOP Access Type: Read/Write Offset: 0x08 Reset Value: 0xFFFFFFFF • VAL[31:0]: RTC Top Value VAL wraps at this value. 32059L–AVR32–01/2012 VAL[31:24 VAL[23:16] ...
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Interrupt Enable Register Name: IER Access Type: Write-only Offset: 0x10 Reset Value: 0x00000000 Writing a zero to a bit in this register has ...
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Interrupt Disable Register Name: IDR Access Type: Write-only Offset: 0x14 Reset Value: 0x00000000 Writing a zero to a bit in this register has ...
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Interrupt Mask Register Name: IMR Access Type: Read-only Offset: 0x18 Reset Value: 0x00000000 The corresponding interrupt is disabled. 1: The corresponding interrupt ...
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Interrupt Status Register Name: ISR Access Type: Read-only Offset: 0x1C Reset Value: 0x00000000 • TOPI: Top Interrupt This bit is set when VAL ...
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Interrupt Clear Register Name: ICR Access Type: Write-only Offset: 0x20 Reset Value: 0x00000000 Writing a zero to a bit in this register has ...
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Watchdog Timer (WDT) Rev: 2.3.1.1 11.1 Features • Watchdog timer counter with 32-bit prescaler • Clocked from the system RC oscillator (RCSYS) 11.2 Overview The Watchdog Timer (WDT) has a prescaler generating a time-out period. This prescaler is clocked ...
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Functional Description The WDT is enabled by writing a one to the Enable bit in the Control register (CTRL.EN). This also enables the system RC clock (CLK_RCSYS) for the prescaler. The Prescale Select field (PSEL) in the CTRL register ...
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Control Register Name: CTRL Access Type: Read/Write Offset: 0x00 Reset Value: 0x00000000 • KEY: Write protection key This field must be written twice, first with ...
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Clear Register Name: CLR Access Type: Write-only Offset: 0x04 Reset Value: 0x00000000 • CLR: Writing periodically any value to this field when the WDT is enabled, within the watchdog time-out period, ...
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Interrupt Controller (INTC) Rev: 1.0.1.5 12.1 Features • Autovectored low latency interrupt service with programmable priority – 4 priority levels for regular, maskable interrupts – One Non-Maskable Interrupt • groups of interrupts with ...
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Figure 12-1. INTC Block Diagram NMIREQ IREQ63 IREQ34 IREQ33 IREQ32 IREQ31 IREQ2 IREQ1 IREQ0 12.4 Product Dependencies In order to use this module, other parts of the system must be configured correctly, as described below. 12.4.1 Power Management If the ...
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Interrupt Priority Register (IPR). The GrpReq inputs are then masked by the mask bits from the CPU status register. Any interrupt group that has a pending interrupt of a priority level that is not masked by the CPU status register, ...
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pipeline stall, which prevents the interrupt from accidentally re-triggering in case the handler is exited and the interrupt mask is cleared before the interrupt request is cleared. 32059L–AVR32–01/2012 91 ...
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User Interface Table 12-1. INTC Register Memory Map Offset Register 0x000 Interrupt Priority Register 0 0x004 Interrupt Priority Register 1 ... 0x0FC Interrupt Priority Register 63 0x100 Interrupt Request Register 0 0x104 Interrupt Request Register 1 ... 0x1FC Interrupt ...
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Interrupt Priority Registers Name: IPR0...IPR63 Access Type: Read/Write Offset: 0x000 - 0x0FC Reset Value: 0x00000000 31 30 INTLEVEL • INTLEVEL: Interrupt Level Indicates the EVBA-relative offset of the interrupt ...
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Interrupt Request Registers Name: IRR0...IRR63 Access Type: Read-only Offset: 0x0FF - 0x1FC Reset Value: N IRR[32*x+31] IRR[32*x+30] IRR[32*x+29 IRR[32*x+23] IRR[32*x+22] IRR[32*x+21 IRR[32*x+15] IRR[32*x+14] IRR[32*x+13 IRR[32*x+7] IRR[32*x+6] IRR[32*x+5] • IRR: Interrupt Request ...
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Interrupt Cause Registers Name: ICR0...ICR3 Access Type: Read-only Offset: 0x200 - 0x20C Reset Value: N • CAUSE: Interrupt Group Causing Interrupt of Priority ...
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Interrupt Request Signal Map The various modules may output Interrupt request signals. These signals are routed to the Inter- rupt Controller (INTC), described in a later chapter. The Interrupt Controller supports groups of interrupt requests. Each ...
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Table 12-2. 32059L–AVR32–01/2012 Interrupt Request Signal Map Universal Synchronous/Asynchronous 6 0 Receiver/Transmitter Universal Synchronous/Asynchronous 7 0 Receiver/Transmitter 9 0 Serial Peripheral Interface 11 0 Two-wire Interface 12 0 Pulse Width Modulation Controller 13 0 Synchronous Serial Controller 0 Timer/Counter 14 ...
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External Interrupt Controller (EIC) Rev: 2.3.1.0 13.1 Features • Dedicated interrupt request for each interrupt • Individually maskable interrupts • Interrupt on rising or falling edge • Interrupt on high or low level • Asynchronous interrupts for sleep modes ...
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Block Diagram Figure 13-1. EIC Block Diagram ...
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Clocks The clock for the EIC bus interface (CLK_EIC) is generated by the Power Manager. This clock is enabled at reset, and can be disabled in the Power Manager. The filter and synchronous edge/level detector runs on a clock ...
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However, the corresponding bit in ISR will be set, and EIC_WAKE will be set. If the CTRL.INTn bit is zero, then the corresponding bit in ISR will always be zero. Disabling an external interrupt by ...
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Non-Maskable Interrupt The NMI supports the same features as the external interrupts, and is accessed through the same registers. The description in instead of the INTn bits. The NMI is non-maskable within the CPU in the sense that it ...
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Keypad scan support The External Interrupt Controller also includes support for keypad scanning. The keypad scan feature is compatible with keypads organized as rows and columns, where a row is shorted against a column when a key is pressed. ...
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User Interface Table 13-2. EIC Register Memory Map Offset 0x000 Interrupt Enable Register 0x004 Interrupt Disable Register 0x008 Interrupt Mask Register 0x00C Interrupt Status Register 0x010 Interrupt Clear Register 0x014 0x018 0x01C 0x020 0x024 0x028 Asynchronous Register 0x2C 0x030 ...
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Interrupt Enable Register Name: IER Access Type: Write-only Offset: 0x000 Reset Value: 0x00000000 INT7 INT6 • INTn: External Interrupt n Writing a zero to this ...
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Interrupt Disable Register Name: IDR Access Type: Write-only Offset: 0x004 Reset Value: 0x00000000 INT7 INT6 • INTn: External Interrupt n Writing a zero to this ...
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Interrupt Mask Register Name: IMR Access Type: Read-only Offset: 0x008 Reset Value: 0x00000000 INT7 INT6 • INTn: External Interrupt n 0: The corresponding interrupt is ...
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Interrupt Status Register Name: ISR Access Type: Read-only Offset: 0x00C Reset Value: 0x00000000 INT7 INT6 • INTn: External Interrupt interrupt event has ...
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Interrupt Clear Register Name: ICR Access Type: Write-only Offset: 0x010 Reset Value: 0x00000000 INT7 INT6 • INTn: External Interrupt n Writing a zero to this ...
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Mode Register Name: MODE Access Type: Read/Write Offset: 0x014 Reset Value: 0x00000000 INT7 INT6 • INTn: External Interrupt n 0: The external interrupt is edge ...
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Edge Register Name: EDGE Access Type: Read/Write Offset: 0x018 Reset Value: 0x00000000 INT7 INT6 • INTn: External Interrupt n 0: The external interrupt triggers on ...
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Level Register Name: LEVEL Access Type: Read/Write Offset: 0x01C Reset Value: 0x00000000 INT7 INT6 • INTn: External Interrupt n 0: The external interrupt triggers on ...
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Filter Register Name: FILTER Access Type: Read/Write Offset: 0x020 Reset Value: 0x00000000 INT7 INT6 • INTn: External Interrupt n 0: The external interrupt is not ...
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Test Register Name: TEST Access Type: Read/Write Offset: 0x024 Reset Value: 0x00000000 INT7 INT6 • TESTEN: Test Enable 0: This bit disables external interrupt test ...
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Asynchronous Register Name: ASYNC Access Type: Read/Write Offset: 0x028 Reset Value: 0x00000000 INT7 INT6 • INTn: External Interrupt n 0: The external interrupt is synchronized ...
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Scan Register Name: SCAN Access Type: Read/Write Offset: 0x2C Reset Value: 0x0000000 • Keypad scanning is disabled 1: Keypad scanning is ...
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Enable Register Name: EN Access Type: Write-only Offset: 0x030 Reset Value: 0x00000000 INT7 INT6 • INTn: External Interrupt n Writing a zero to this bit ...
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Disable Register Name: DIS Access Type: Write-only Offset: 0x034 Reset Value: 0x00000000 INT7 INT6 • INTn: External Interrupt n Writing a zero to this bit ...
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Control Register Name: CTRL Access Type: Read-only Offset: 0x038 Reset Value: 0x00000000 INT7 INT6 • INTn: External Interrupt n 0: The corresponding external interrupt is ...
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Flash Controller (FLASHC) Rev: 2.1.2.4 14.1 Features • Controls flash block with dual read ports allowing staggered reads. • Supports 0 and 1 wait state bus access. • Allows interleaved burst reads for systems with one wait state, outputting ...
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Functional description 14.4.1 Bus interfaces The FLASHC has two bus interfaces, one HSB interface for reads from the flash array and writes to the page buffer, and one Peripheral Bus (PB) interface for writing commands and con- trol to ...
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The flash controller supports flash blocks with up to 2^21 word addresses, as displayed in 14-1. Reading the memory space between address pw and 2^21-1 returns an undefined result. The User page is permanently mapped to word address 2^21. Table ...
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The page buffer is also used for writes to the User page. Write operations can be prevented by programming the Memory Protection Unit of the CPU. Writing 8-bit and 16-bit data to the page buffer is not allowed and may ...
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All the commands are protected by the same keyword, which has to be written in the eight high- est bits of FCMD. Writing FCMD with data that does not contain the correct key and/or with an invalid command has no ...
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The EA command also ensures that all volatile memories, such as register file and RAMs, are erased before the security bit is erased. Erase All operation is allowed only if no regions are locked, and the BOOTPROT fuses are pro- ...
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Peripheral Bus address. Some of the general-purpose fuse bits are reserved for special purposes, and should not be used for other functions.: Table 14-2. General- Purpose fuse number 15:0 16 19:17 The BOOTPROT fuses protects the following ...
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To erase or write a general-purpose fuse bit, the commands Write General-Purpose Fuse Bit (WGPB) and Erase General-Purpose Fuse Bit (EGPB) are provided. Writing one of these com- mands, together with the number of the fuse to write/erase, performs the ...
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User Interface Table 14-4. FLASHC Register Memory Map Offset Register 0x0 Flash Control Register 0x4 Flash Command Register 0x8 Flash Status Register 0xc Flash General Purpose Fuse Register Hi 0x10 Flash General Purpose Fuse Register Lo (*) The value ...
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Flash Control Register Name: FCR Access Type: Read/Write Offset: 0x00 Reset value: 0x00000000 FWS • FRDY: Flash Ready Interrupt Enable 0: Flash Ready does ...
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Flash Command Register Name: FCMD Access Type: Read/Write Offset: 0x04 Reset value: 0x00000000 FCMD can not be written if the flash is in the process of performing a flash command. Doing so will cause the FCR write to be ...
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Table 14-5. Set of commands Command Write User Page Erase User Page Quick Page Read User Page • PAGEN: Page number The PAGEN field is used to address a page or fuse bit for certain operations. In order to simplify ...
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Flash Status Register Name: FSR Access Type: Read/Write Offset: 0x08 Reset value: 0x00000000 31 30 LOCK15 LOCK14 23 22 LOCK7 LOCK6 15 14 FSZ • FRDY: Flash Ready Status 0: The flash controller is busy ...
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FSZ: Flash Size The size of the flash. Not all device families will provide all flash sizes indicated in the table. Table 14-7. Flash size FSZ Flash Size 0 32 Kbytes 1 64 Kbytes 2 128 Kbytes 3 256 ...
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Flash General Purpose Fuse Register High Name: FGPFRHI Access Type: Read Offset: 0x0C Reset value: N GPF63 GPF62 23 22 GPF55 GPF54 15 14 GPF47 GPF46 7 6 GPF39 GPF38 This register is only used in systems ...
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Flash General Purpose Fuse Register Low Name: FGPFRLO Access Type: Read Offset: 0x10 Reset value: N GPF31 GPF30 23 22 GPF23 GPF22 15 14 GPF15 GPF14 7 6 GPF07 GPF06 • GPFxx: General Purpose Fuse xx 0: ...
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Fuses Settings The flash block contains a number of general purpose fuses. Some of these fuses have defined meanings outside the flash controller and are described in this section. The general purpose fuses are erase by a JTAG chip ...
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... Flash Size Part Number (FLASH_PW) AT32UC3B0512 512 Kbytes AT32UC3B1512 512 Kbytes AT32UC3B0256 256 Kbytes AT32UC3B1256 256 Kbytes AT32UC3B0128 128 Kbytes AT32UC3B1128 128 Kbytes AT32UC3B064 64 Kbytes AT32UC3B164 64 Kbytes 32059L–AVR32–01/2012 Number of pages Page size (FLASH_P) (FLASH_W) 1024 128 words 1024 ...
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HSB Bus Matrix (HMATRIX) Rev: 2.3.0.2 15.1 Features • User Interface on peripheral bus • Configurable Number of Masters (Up to sixteen) • Configurable Number of Slaves (Up to sixteen) • One Decoder for Each Master • • Programmable ...
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At the end of the current access other request is pending, the slave remains connected to its associated default master. A slave can be associated with three kinds of default masters: no default master, last access master and ...
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End of Burst Cycles: When the current cycle is the last cycle of a burst transfer. For defined length burst, predicted end of burst matches the size of the transfer but is man- aged differently for undefined length burst. ...
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This configuration incurs one latency cycle for the first access of a burst. Arbitration without default master can be used for masters that perform ...
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User Interface Table 15-1. HMATRIX Register Memory Map Offset Register 0x0000 Master Configuration Register 0 0x0004 Master Configuration Register 1 0x0008 Master Configuration Register 2 0x000C Master Configuration Register 3 0x0010 Master Configuration Register 4 0x0014 Master Configuration Register ...
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Table 15-1. HMATRIX Register Memory Map (Continued) Offset Register 0x008C Priority Register B for Slave 1 0x0090 Priority Register A for Slave 2 0x0094 Priority Register B for Slave 2 0x0098 Priority Register A for Slave 3 0x009C Priority Register ...
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Table 15-1. HMATRIX Register Memory Map (Continued) Offset Register 0x012C Special Function Register 7 0x0130 Special Function Register 8 0x0134 Special Function Register 9 0x0138 Special Function Register 10 0x013C Special Function Register 11 0x0140 Special Function Register 12 0x0144 ...
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Master Configuration Registers Name: MCFG0...MCFG15 Access Type: Read/Write Offset: 0x00 - 0x3C Reset Value: 0x00000002 31 30 – – – – – – – – • ULBT: Undefined Length Burst Type 0: Infinite ...
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Slave Configuration Registers Name: SCFG0...SCFG15 Access Type: Read/Write Offset: 0x40 - 0x7C Reset Value: 0x00000010 31 30 – – – – – – • ARBT: Arbitration Type 0: Round-Robin Arbitration 1: Fixed Priority ...
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Priority Registers A For Slaves Name: PRAS0...PRAS15 Access Type: Read/Write Offset: - Reset Value: 0x00000000 31 30 – – – – – – – – • MxPR: Master x Priority Fixed priority of ...
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Priority Registers B For Slaves Name: PRBS0...PRBS15 Access Type: Read/Write Offset: - Reset Value: 0x00000000 31 30 – – – – – – – – • MxPR: Master x Priority Fixed priority of ...
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Special Function Registers Name: Access Type: Offset: 0x110 - 0x115 Reset Value • SFR: Special Function Register Fields Those registers are not a HMATRIX specific register. The field of those ...
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Bus Matrix Connections Accesses to unused areas returns an error result to the master requesting such an access. The bus matrix has the several masters and slaves. Each master has its own bus and its own decoder, thus allowing ...
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Figure 15-1. HMatrix Master / Slave Connections 32059L–AVR32–01/2012 HMATRIX SLAVES 0 1 CPU Data 0 CPU 1 Instruction CPU SAB 2 PDCA 3 USBB DMA 151 ...
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Peripheral DMA Controller (PDCA) Rev: 1.0.2.1 16.1 Features • Multiple channels • Generates transfers between memories and peripherals such as USART and SPI • Two address pointers/counters per channel allowing double buffering 16.2 Overview The Peripheral DMA Controller (PDCA) ...
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Block Diagram Figure 16-1. PDCA Block Diagram High Speed Bus Matrix Controller 16.4 Product Dependencies In order to use this module, other parts of the system must be configured correctly, as described below. 16.4.1 Power Management If the CPU ...
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Functional Description 16.5.1 Basic Operation The PDCA consists of multiple independent PDCA channels, each capable of handling DMA requests in parallel. Each PDCA channels contains a set of configuration registers which must be configured to start a DMA transfer. ...
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Peripheral Selection The Peripheral Select Register (PSR) decides which peripheral should be connected to the PDCA channel. A peripheral is selected by writing the corresponding Peripheral Identity (PID) to the PID field in the PSR register. Writing the PID ...
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Interrupt Status Register (ISR.TERR) will be set and the DMA channel that caused the error will be stopped. In order to restart the channel, the user must program the Memory Address Register to a valid address and ...
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User Interface 16.6.1 Memory Map Overview Table 16-1. PDCA Register Memory Map Address Range 0x000 - 0x03F 0x040 - 0x07F ... (0x000 - 0x03F)+m*0x040 The channels are mapped as shown in isters, shown in 16.6.2 Channel Memory Map Table ...
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Memory Address Register Name: MAR Access Type: Read/Write Offset: 0x000 + n*0x040 Reset Value: 0x00000000 • MADDR: Memory Address Address of memory buffer. MADDR should be programmed to point to the ...
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Peripheral Select Register Name: PSR Access Type: Read/Write Offset: 0x004 + n*0x040 Reset Value • PID: Peripheral Identifier The Peripheral Identifier selects which peripheral ...
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Transfer Counter Register Name: TCR Access Type: Read/Write Offset: 0x008 + n*0x040 Reset Value: 0x00000000 • TCV: Transfer Counter Value Number of data items to be transferred ...
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Memory Address Reload Register Name: MARR Access Type: Read/Write Offset: 0x00C + n*0x040 Reset Value: 0x00000000 • MARV: Memory Address Reload Value Reload Value for the MAR register. This value will ...
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Transfer Counter Reload Register Name: TCRR Access Type: Read/Write Offset: 0x010 + n*0x040 Reset Value: 0x00000000 • TCRV: Transfer Counter Reload Value Reload value for the TCR ...
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Control Register Name: CR Access Type: Write-only Offset: 0x014 + n*0x040 Reset Value: 0x00000000 • ECLR: Transfer Error Clear Writing a zero to ...
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Mode Register Name: MR Access Type: Read/Write Offset: 0x018 + n*0x040 Reset Value: 0x00000000 • SIZE: Size of Transfer Table 16-3. Size of ...
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Status Register Name: SR Access Type: Read-only Offset: 0x01C + n*0x040 Reset Value: 0x00000000 • TEN: Transfer Enabled This bit is cleared when ...
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Interrupt Enable Register Name: IER Access Type: Write-only Offset: 0x020 + n*0x040 Reset Value: 0x00000000 Writing a zero to a bit in this ...
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Interrupt Disable Register Name: IDR Access Type: Write-only Offset: 0x024 + n*0x040 Reset Value: 0x00000000 Writing a zero to a bit in this ...
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Interrupt Mask Register Name: IMR Access Type: Read-only Offset: 0x028 + n*0x040 Reset Value: 0x00000000 The corresponding interrupt is disabled. 1: The ...
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Interrupt Status Register Name: ISR Access Type: Read-only Offset: 0x02C + n*0x040 Reset Value: 0x00000000 • TERR: Transfer Error This bit is cleared ...
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Module Configuration The specific configuration for the PDCA instance is listed in the following tables. Table 16-4. Features Number of channels Table 16-5. Register PSRn 16.7.1 DMA Handshake Signals The following table defines the valid settings for the Peripheral ...
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General-Purpose Input/Output Controller (GPIO) Rev: 1.1.0.4 17.1 Features Each I/O line of the GPIO features: • Configurable pin-change, rising-edge or falling-edge interrupt on any I/O line • A glitch filter providing rejection of pulses shorter than one clock cycle ...
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Module Configuration Most of the features of the GPIO are configurable for each product. The user must refer to the Package and Pinout chapter for these settings. Product specific settings includes: • Number of I/O pins. • Functions implemented ...
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Figure 17-2. Overview of the GPIO Pad Connections Periph. A output enable Periph. B output enable Periph. C output enable Periph. D output enable Periph. A output data Periph. B output data Periph. C output data Periph. D output data ...
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I/O line is driven by the GPIO. When the bit is written to zero, the GPIO does not drive the line. The level driven on an I/O line can be determined by writing to the Output Value Register (OVR). ...
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Interrupts The GPIO can be configured to generate an interrupt when it detects an input change on an I/O line. The module can be configured to signal an interrupt whenever a pin changes value or only to trigger on ...
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User Interface The GPIO controls all the I/O pins on the AVR32 microcontroller. The pins are managed as 32- bit ports that are configurable through a PB interface. Each port has a set of configuration regis- ters. The overall ...
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GPIO start address. One bit in each of the configuration registers corresponds to an I/O pin. Table 17-1. Offset 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x40 ...
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Table 17-1. Offset 0xB4 0xB8 0xBC 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 1) The reset value for these registers are device specific. Please refer to the Module Config- uration section at the end of this chapter. 2) The ...
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Enable Register Name: GPER Access Type: Read, Write, Set, Clear, Toggle Offset: 0x00, 0x04, 0x08, 0x0C Reset Value P31 P30 23 22 P23 P22 15 14 P15 P14 • P0-P31: Pin Enable ...
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Peripheral Mux Register 0 Name: PMR0 Access Type: Read, Write, Set, Clear, Toggle Offset: 0x10, 0x14, 0x18, 0x1C Reset Value P31 P30 23 22 P23 P22 15 14 P15 P14 • P0-31: ...
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Peripheral Mux Register 1 Name: PMR1 Access Type: Read, Write, Set, Clear, Toggle Offset: 0x20, 0x24, 0x28, 0x2C Reset Value P31 P30 23 22 P23 P22 15 14 P15 P14 • P0-31: ...
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Output Driver Enable Register Name: ODER Access Type: Read, Write, Set, Clear, Toggle Offset: 0x40, 0x44, 0x48, 0x4C Reset Value P31 P30 23 22 P23 P22 15 14 P15 P14 • P0-31: ...
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Output Value Register Name: OVR Access Type: Read, Write, Set, Clear, Toggle Offset: 0x50, 0x54, 0x58, 0x5C Reset Value P31 P30 23 22 P23 P22 15 14 P15 P14 • P0-31: Output ...
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Pin Value Register Name: PVR Access Type: Read Offset: 0x60, 0x64, 0x68, 0x6C Reset Value P31 P30 23 22 P23 P22 15 14 P15 P14 • P0-31: Pin Value 0: The I/O ...
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Pull-up Enable Register Name: PUER Access Type: Read, Write, Set, Clear, Toggle Offset: 0x70, 0x74, 0x78, 0x7C Reset Value P31 P30 23 22 P23 P22 15 14 P15 P14 • P0-31: Pull-up ...
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Interrupt Enable Register Name: IER Access Type: Read, Write, Set, Clear, Toggle Offset: 0x90, 0x94, 0x98, 0x9C Reset Value P31 P30 23 22 P23 P22 15 14 P15 P14 • P0-31: Interrupt ...
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Interrupt Mode Register 0 Name: IMR0 Access Type: Read, Write, Set, Clear, Toggle Offset: 0xA0, 0xA4, 0xA8, 0xAC Reset Value P31 P30 23 22 P23 P22 15 14 P15 P14 • P0-31: ...
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Interrupt Mode Register 1 Name: IMR1 Access Type: Read, Write, Set, Clear, Toggle Offset: 0xB0, 0xB4, 0xB8, 0xBC Reset Value P31 P30 23 22 P23 P22 15 14 P15 P14 • P0-31: ...
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Glitch Filter Enable Register Name: GFER Access Type: Read, Write, Set, Clear, Toggle Offset: 0xC0, 0xC4, 0xC8, 0xCC Reset Value P31 P30 23 22 P23 P22 15 14 P15 P14 • P0-31: ...
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Interrupt Flag Register Name: IFR Access Type: Read, Clear Offset: 0xD0, 0xD8 Reset Value P31 P30 23 22 P23 P22 15 14 P15 P14 • P0-31: Interrupt Flag 1: An interrupt condition ...
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Programming Examples 17.7.1 8-bit LED-Chaser loop assumed in this example that a subroutine "delay" exists that returns after a given time. 17.7.2 Configuration of USART pins The example below shows how to configure a peripheral module to ...
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R1, 0x0000 orh R1, 0x0003 st.w R0[AVR32_GPIO_ODERC Make the GPIO control the pins st.w R0[AVR32_GPIO_GPERS Select peripheral B on PC16-PC17 st.w R0[AVR32_GPIO_PMR0S], R1 st.w R0[AVR32_GPIO_PMR1C Enable peripheral control st.w R0[AVR32_GPIO_GPERC], R1 192 ...
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Module Configuration The specific configuration for each GPIO instance is listed in the following tables. The module bus clocks listed here are connected to the system bus clocks. Refer to the Power Manager chapter for details. Table 17-2. Feature ...
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Serial Peripheral Interface (SPI) Rev. 1.9.9.2 18.1 Features • Supports Communication with Serial External Devices – Four Chip Selects with External Decoder Support Allow Communication with Peripherals – Serial Memories, such as DataFlash and 3-wire EEPROMs ...
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Block Diagram Figure 18-1. Block Diagram Peripheral Bus 18.4 Application Block Diagram Figure 18-2. Application Block Diagram: Single Master/Multiple Slave Implementation Spi Master 32059L–AVR32–01/2012 PDCA CLK_SPI Spi Interface DIV CLK_SPI Interrupt Control 32 SPI Interrupt SPCK MISO MOSI NPCS0 ...
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Signal Description Table 18-1. Pin Name Pin Description MISO Master In Slave Out MOSI Master Out Slave In SPCK Serial Clock NPCS1-NPCS3 Peripheral Chip Selects NPCS0/NSS Peripheral Chip Select/Slave Select 18.6 Product Dependencies 18.6.1 I/O Lines The pins used ...
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NCPHA bit. These two parameters determine the edges of the clock signal on which data is driven and sampled. Each of the two parameters has two possible states, resulting in four possi- ble combinations that are incompatible with one ...
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Master Mode Operations When configured in Master Mode, the SPI uses the internal programmable baud rate generator as clock source. It fully controls the data transfers to and from the slave(s) connected to the SPI bus. The SPI drives ...
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Master Mode Block Diagram Figure 18-5. Master Mode Block Diagram CLK_SPI MISO MR TDR NPCS0 32059L–AVR32–01/2012 CSR0..3 SCBR Baud Rate Generator SPI Clock CSR0..3 BITS NCPHA CPOL LSB Shift Register TDR CSR0..3 CSAAT PS PCSDEC PCS Current 0 Peripheral ...
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Master Mode Flow Diagram Figure 18-6. Master Mode Flow Diagram 32059L–AVR32–01/2012 200 ...