AT32UC3B1128 Atmel Corporation, AT32UC3B1128 Datasheet - Page 3

• Manufacturer Part Number: AT32UC3B1128
• Manufacturer: Atmel Corporation

Specifications of AT32UC3B1128

• Flash (kbytes): 128 Kbytes
• Pin Count: 48
• Max. Operating Frequency: 60 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 28
• Ext Interrupts: 28
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 3
• Twi (i2c): 1
• Uart: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 6
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0-3.6 or (1.65-1.95+3.0-3.6)
• Operating Voltage (vcc): 3.0-3.6 or (1.65-1.95+3.0-3.6)
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 10
• Output Compare Channels: 16
• Input Capture Channels: 6
• Pwm Channels: 13
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

1.3
1.4
1.5
1.6
32002F–03/2010
Exceptions and Interrupts
Java Support
FlashVault
Microarchitectures
The register file is organized as 16 32-bit registers and includes the Program Counter, the Link
Register, and the Stack Pointer. In addition, one register is designed to hold return values from
function calls and is used implicitly by some instructions.
The AVR32 core defines several micro architectures in order to capture the entire range of appli-
cations. The microarchitectures are named AVR32A, AVR32B and so on. Different
microarchitectures are suited to different end applications, allowing the designer to select a
microarchitecture with the optimum set of parameters for a specific application.
The AVR32 incorporates a powerful exception handling scheme. The different exception
sources, like Illegal Op-code and external interrupt requests, have different priority levels, ensur-
ing a well-defined behavior when multiple exceptions are received simultaneously. Additionally,
pending exceptions of a higher priority class may preempt handling of ongoing exceptions of a
lower priority class. Each priority class has dedicated registers to keep the return address and
status register thereby removing the need to perform time-consuming memory operations to
save this information.
There are four levels of external interrupt requests, all executing in their own context. An inter-
rupt controller does the priority handling of the external interrupts and provides the prioritized
interrupt vector to the processor core.
Some AVR32 implementations provide Java hardware acceleration. To reduce gate count,
AVR32UC does not implement any such hardware.
Revision 3 of the AVR32 architecture introduced a new CPU state called Secure State. This
state is instrumental in the new security technology named FlashVault. This innovation allows
the on-chip flash and other memories to be partially programmed and locked, creating a safe on-
chip storage for secret code and valuable software intellectual property. Code stored in the
FlashVault will execute as normal, but reading, copying or debugging the code is not possible.
This allows a device with FlashVault code protection to carry a piece of valuable software such
as a math library or an encryption algorithm from a trusted location to a potentially untrustworthy
partner where the rest of the source code can be developed, debugged and programmed.
The AVR32 architecture defines different microarchitectures, AVR32A and AVR32B. This
enables implementations that are tailored to specific needs and applications. The microarchitec-
tures provide different performance levels at the expense of area and power consumption.
The AVR32A microarchitecture is targeted at cost-sensitive, lower-end applications like smaller
microcontrollers. This microarchitecture does not provide dedicated hardware registers for shad-
owing of register file registers in interrupt contexts. Additionally, it does not provide hardware
registers for the return address registers and return status registers. Instead, all this information
is stored on the system stack. This saves chip area at the expense of slower interrupt handling.
• Load/store to an address specified by a small immediate (direct addressing within a small
• Load/store to an address specified by a pointer register and an index register.
page)
AVR32
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