AT32UC3A1512AU Atmel Corporation, AT32UC3A1512AU Datasheet - Page 619

• Manufacturer Part Number: AT32UC3A1512AU
• Manufacturer: Atmel Corporation

Specifications of AT32UC3A1512AU

• Flash (kbytes): 512 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 69
• Ext Interrupts: 69
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device + OTG
• Spi: 6
• Twi (i2c): 1
• Uart: 4
• Ssc: 1
• Ethernet: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 16
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0-3.6 or (1.65-1.95+3.0-3.6)
• Operating Voltage (vcc): 3.0-3.6 or (1.65-1.95+3.0-3.6)
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 10
• Output Compare Channels: 16
• Input Capture Channels: 6
• Pwm Channels: 13
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

32058K AVR32-01/12
• CURRBK: Current Bank
For non-control pipe, set by hardware to indicate the number of the current bank.
Note that this field may be updated 1 clock cycle after the RWALL bit changes, so the user should not poll this field as an
interrupt flag.
• RWALL: Read/Write Allowed
For OUT pipe, set by hardware when the current bank is not full, i.e. the software can write further data into the FIFO.
For IN pipe, set by hardware when the current bank is not empty, i.e. the software can read further data from the FIFO.
Cleared by hardware otherwise.
This bit is also cleared by hardware when the RXSTALL or the PERR bit is set.
• CFGOK: Configuration OK Status
This bit is updated when the ALLOC bit is set.
Set by hardware if the pipe X number of banks (PBK) and size (PSIZE) are correct compared to the maximal allowed num-
ber of banks and size for this pipe and to the maximal FIFO size (i.e. the DPRAM size).
If this bit is cleared by hardware, the user should reprogram the UPCFGX register with correct PBK and PSIZE values.
• PBYCT: Pipe Byte Count
Set by the hardware to indicate the byte count of the FIFO.
For OUT pipe, incremented after each byte written by the software into the pipe and decremented after each byte sent to
the peripheral.
For In pipe, incremented after each byte received from the peripheral and decremented after each byte read by the soft-
ware from the pipe.
Note that this field may be updated 1 clock cycle after the RWALL bit changes, so the user should not poll this field as an
interrupt flag.
0
0
1
1
CURRBK
0
1
0
1
Current Bank
Bank0
Bank1
Bank2
Reserved
AT32UC3A
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