AT32UC3A1512AU Atmel Corporation, AT32UC3A1512AU Datasheet - Page 187

• Manufacturer Part Number: AT32UC3A1512AU
• Manufacturer: Atmel Corporation

Specifications of AT32UC3A1512AU

• Flash (kbytes): 512 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 69
• Ext Interrupts: 69
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device + OTG
• Spi: 6
• Twi (i2c): 1
• Uart: 4
• Ssc: 1
• Ethernet: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 16
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0-3.6 or (1.65-1.95+3.0-3.6)
• Operating Voltage (vcc): 3.0-3.6 or (1.65-1.95+3.0-3.6)
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 10
• Output Compare Channels: 16
• Input Capture Channels: 6
• Pwm Channels: 13
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

32058K AVR32-01/12
22.5.13
Name:
Access:
• P0-31: Glitch Filter Enable
0 = Glitch filter is disabled for the corresponding pin.
1 = Glitch filter is enabled for the corresponding pin.
NOTE! The value of this register should only be changed when IER is ‘0’. Updating this GFER while interrupt on the corre-
sponding pin is enabled can cause an unintentional interrupt to be triggered.
P31
P23
P15
P7
31
23
15
7
Glitch Filter Enable Register
GFER
Read, Write, Set, Clear, Toggle
P30
P22
P14
P6
30
22
14
6
P29
P21
P13
P5
29
21
13
5
P28
P20
P12
P4
28
20
12
4
P27
P19
P11
P3
27
19
11
3
P26
P18
P10
P2
26
18
10
2
P25
P17
P9
P1
25
17
9
1
AT32UC3A
P24
P16
P8
P0
24
16
8
0
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