AT32UC3A1512AU Atmel Corporation, AT32UC3A1512AU Datasheet - Page 613

• Manufacturer Part Number: AT32UC3A1512AU
• Manufacturer: Atmel Corporation

Specifications of AT32UC3A1512AU

• Flash (kbytes): 512 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 69
• Ext Interrupts: 69
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device + OTG
• Spi: 6
• Twi (i2c): 1
• Uart: 4
• Ssc: 1
• Ethernet: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 16
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0-3.6 or (1.65-1.95+3.0-3.6)
• Operating Voltage (vcc): 3.0-3.6 or (1.65-1.95+3.0-3.6)
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 10
• Output Compare Channels: 16
• Input Capture Channels: 6
• Pwm Channels: 13
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

32058K AVR32-01/12
30.8.3.11
Offset:
Register Name:
Access Type:
Reset Value:
• PENX, X in [0..6]: Pipe X Enable
Set to enable the Pipe X.
Clear to disable the Pipe X, what forces the Pipe X state to inactive and resets the pipe X registers (UPCFGX, UPSTAX,
UPCONX) but not the pipe configuration (ALLOC, PBK, PSIZE).
• PRSTX, X in [0..6]: Pipe X Reset
Set by software to reset the Pipe X FIFO.
This resets the endpoint X registers (UPCFGX, UPSTAX, UPCONX) but not the endpoint configuration (ALLOC, PBK,
PSIZE, PTOKEN, PTYPE, PEPNUM, INTFRQ).
All the endpoint mechanism (FIFO counter, reception, transmission, etc.) is reset apart from the Data Toggle management
.
The endpoint configuration remains active and the endpoint is still enabled.
Then, clear by software to complete the reset operation and to start using the FIFO.
31
23
15
–
–
–
7
–
USB Pipe Enable/Reset Register (UPRST)
PRST6
PEN6
rwu
30
22
14
rw
–
0
–
6
0
PRST5
PEN5
rwu
29
21
13
rw
–
0
–
5
0
0x0041C
UPRST
Read/Write
0x00000000
PRST4
PEN4
rwu
28
20
12
rw
–
0
–
4
0
PRST3
PEN3
rwu
27
19
11
rw
–
0
–
3
0
PRST2
PEN2
rwu
26
18
10
rw
–
0
–
2
0
PRST1
PEN1
rwu
25
17
rw
–
0
9
–
1
0
AT32UC3A
PRST0
PEN0
rwu
24
16
rw
–
0
8
–
0
0
613