AT32UC3A1512AU Atmel Corporation, AT32UC3A1512AU Datasheet - Page 451

• Manufacturer Part Number: AT32UC3A1512AU
• Manufacturer: Atmel Corporation

Specifications of AT32UC3A1512AU

• Flash (kbytes): 512 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 69
• Ext Interrupts: 69
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device + OTG
• Spi: 6
• Twi (i2c): 1
• Uart: 4
• Ssc: 1
• Ethernet: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 16
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0-3.6 or (1.65-1.95+3.0-3.6)
• Operating Voltage (vcc): 3.0-3.6 or (1.65-1.95+3.0-3.6)
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 10
• Output Compare Channels: 16
• Input Capture Channels: 6
• Pwm Channels: 13
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

32058K AVR32-01/12
29.6
29.6.1
29.6.1.1
29.6.1.2
Figure 29-2. Receive Buffer List
Programming Interface
Initialization
Configuration
Receive Buffer List
Receive Buffer Queue Pointer
(MAC Register)
Initialization of the MACB configuration (e.g. frequency ratios) must be done while the transmit
and receive circuits are disabled. See the description of the network control register and network
configuration register later in this document.
Receive data is written to areas of data (i.e., buffers) in system memory. These buffers are listed
in another data structure that also resides in main memory. This data structure (receive buffer
queue) is a sequence of descriptor entries as defined in
page
To create the list of buffers:
1. Allocate a number (n) of buffers of 128 bytes in system memory.
2. Allocate an area 2n words for the receive buffer descriptor entry in system memory and
3. If less than 1024 buffers are defined, the last descriptor must be marked with the wrap bit
4. Write address of receive buffer descriptor entry to MACB register receive_buffer queue
5. The receive circuits can then be enabled by writing to the address recognition registers
create n entries in this list. Mark all entries in this list as owned by MACB, i.e., bit 0 of
word 0 set to 0.
(bit 1 in word 0 set to 1).
pointer.
and then to the network control register.
440. It points to this data structure.
Receive Buffer Descriptor List
(In memory)
”Receive Buffer Descriptor Entry” on
Receive Buffer 1
Receive Buffer 0
Receive Buffer N
(In memory)
AT32UC3A
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