AT32UC3A1512AU Atmel Corporation, AT32UC3A1512AU Datasheet - Page 584

• Manufacturer Part Number: AT32UC3A1512AU
• Manufacturer: Atmel Corporation

Specifications of AT32UC3A1512AU

• Flash (kbytes): 512 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 69
• Ext Interrupts: 69
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device + OTG
• Spi: 6
• Twi (i2c): 1
• Uart: 4
• Ssc: 1
• Ethernet: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 16
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0-3.6 or (1.65-1.95+3.0-3.6)
• Operating Voltage (vcc): 3.0-3.6 or (1.65-1.95+3.0-3.6)
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 10
• Output Compare Channels: 16
• Input Capture Channels: 6
• Pwm Channels: 13
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

AT32UC3A
Clear by software (by setting the FIFOCONC bit) to free the current bank and to switch to the next bank.
• EPDISHDMA: Endpoint Interrupts Disable HDMA Request Enable
Set by software (by setting the EPDISHDMAS bit) to pause the on-going DMA channel X transfer on any Endpoint X inter-
rupt (EPXINT), whatever the state of the Endpoint X Interrupt Enable bit (EPXINTE).
The software then has to acknowledge or to disable the interrupt source (e.g. RXOUTI) or to clear the EPDISHDMA bit (by
setting the EPDISHDMAC bit) in order to complete the DMA transfer.
In ping-pong mode, if the interrupt is associated to a new system-bank packet (e.g. Bank1) and the current DMA transfer is
running on the previous packet (Bank0), then the previous-packet DMA transfer completes normally, but the new-packet
DMA transfer will not start (not requested).
If the interrupt is not associated to a new system-bank packet (NAKINI, NAKOUTI, etc.), then the request cancellation may
occur at any time and may immediately pause the current DMA transfer.
This may be used for example to identify erroneous packets, to prevent them from being transferred into a buffer, to com-
plete a DMA transfer by software after reception of a short packet, etc.
• RSTDT: Reset Data Toggle
Set by software (by setting the RSTDTS bit) to clear the data toggle sequence, i.e. to set to Data0 the data toggle sequence
of the next sent (IN endpoints) or received (OUT endpoints) packet.
Cleared by hardware instantaneously.
The software does not have to wait for this bit to be cleared.
• STALLRQ: STALL Request
Set by software (by setting the STALLRQS bit) to request to send a STALL handshake to the host.
Cleared by hardware when a new SETUP packet is received.
Can also be cleared by software by setting the STALLRQC bit.
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32058K AVR32-01/12