AT32UC3A1512AU Atmel Corporation, AT32UC3A1512AU Datasheet - Page 592

• Manufacturer Part Number: AT32UC3A1512AU
• Manufacturer: Atmel Corporation

Specifications of AT32UC3A1512AU

• Flash (kbytes): 512 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 69
• Ext Interrupts: 69
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device + OTG
• Spi: 6
• Twi (i2c): 1
• Uart: 4
• Ssc: 1
• Ethernet: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 16
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0-3.6 or (1.65-1.95+3.0-3.6)
• Operating Voltage (vcc): 3.0-3.6 or (1.65-1.95+3.0-3.6)
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 10
• Output Compare Channels: 16
• Input Capture Channels: 6
• Pwm Channels: 13
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

32058K AVR32-01/12
30.8.2.18
Offset:
Register Name:
Access Type:
Reset Value:
• HSB_ADDR: HSB Address
This field determines the HSB bus current address of a channel transfer.
The address set on the HSB address bus is HSB_ADDR rounded down to the nearest word-aligned address, i.e.
HSB_ADDR[1:0] is considered as 00b since only word accesses are performed.
Channel HSB start and end addresses may be aligned on any byte boundary.
The software may write this field only when the Channel Enabled bit (CH_EN) of the UDDMAX_STATUS register is clear.
This field is updated at the end of the address phase of the current access to the HSB bus. It is incremented of the HSB
access byte-width.
The HSB access width is 4 bytes, or less at packet start or end if the start or end address is not aligned on a word
boundary.
The packet start address is either the channel start address or the next channel address to be accessed in the channel
buffer.
The packet end address is either the channel end address or the latest channel address accessed in the channel buffer.
The channel start address is written by software or loaded from the descriptor, whereas the channel end address is either
determined by the end of buffer or the end of USB transfer if the Buffer Close Input Enable bit (BUFF_CLOSE_IN_EN) is
set.
31
23
15
0
0
0
7
0
USB Device DMA Channel X HSB Address Register (UDDMAX_ADDR)
30
22
14
0
0
0
6
0
29
21
13
0
0
0
5
0
0x0314 + (X - 1) . 0x10
UDDMAX_ADDR, X in [1..6]
Read/Write
0x00000000
28
20
12
0
0
0
4
0
HSB_ADDR
HSB_ADDR
HSB_ADDR
HSB_ADDR
rwu
rwu
rwu
rwu
27
19
11
0
0
0
3
0
26
18
10
0
0
0
2
0
25
17
0
0
9
0
1
0
AT32UC3A
24
16
0
0
8
0
0
0
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