AT32UC3A1512AU Atmel Corporation, AT32UC3A1512AU Datasheet - Page 147

• Manufacturer Part Number: AT32UC3A1512AU
• Manufacturer: Atmel Corporation

Specifications of AT32UC3A1512AU

• Flash (kbytes): 512 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 69
• Ext Interrupts: 69
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device + OTG
• Spi: 6
• Twi (i2c): 1
• Uart: 4
• Ssc: 1
• Ethernet: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 16
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0-3.6 or (1.65-1.95+3.0-3.6)
• Operating Voltage (vcc): 3.0-3.6 or (1.65-1.95+3.0-3.6)
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 10
• Output Compare Channels: 16
• Input Capture Channels: 6
• Pwm Channels: 13
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

32058K AVR32-01/12
20.4
Table 20-1.
Name
D0 - D15
A0 - A23
NWAIT
NCS0 - NCS3
NWR0 - NWR3
NOE
NRD
NWE
NBS0 - NBS3
SDCK
SDCKE
BA0 - BA1
SDWE
RAS - CAS
NWR0 - NWR3
NBS0 - NBS3
SDA10
I/O Lines Description
EBI I/O Lines Description
Depending on the Memory Controller in use, all signals are not connected directly through the
Mux Logic.
Table 20-2 on page 147
EBI pins.
Table 20-2.
NWR1/NBS1
A0/NBS0
A1/NBS2/NWR2
A[11:2]
SDA10
A12
A[14:13]
External Wait Signal
Chip Select Lines
Output Enable
Read Signal
Write Enable
Byte Mask Signals
SDRAM Clock
SDRAM Clock Enable
Bank Select
Row and Column Signal
Byte Mask Signals
SDRAM Address 10 Line
Function
Data Bus
Address Bus
Write Signals
SDRAM Write Enable
Write Signals
EBI Pins and Memory Controllers I/O Lines Connections
EBI Pins
details the connections between the two Memory Controllers and the
SDRAM Controller
SMC
EBI
NBS1
Not Supported
Not Supported
SDRAMC_A[9:0]
SDRAMC_A10
Not Supported
SDRAMC_A[12:11]
SDRAMC I/O Lines
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Type
Input
I/O
SMC_A[11:2]
SMC_A[14:13]
NWR1/NUB
SMC_A0/NLB
SMC_A1
Not Supported
SMC_A12
AT32UC3A
SMC I/O Lines
Active Level
High
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
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