M28529G-12 Mindspeed Technologies, M28529G-12 Datasheet - Page 83

• Manufacturer Part Number: M28529G-12
• Description: ATM IMA 8.192Mbps 1.8V/3.3V 484-Pin BGA
• Manufacturer: Mindspeed Technologies

Specifications of M28529G-12

• Package: 484BGA
• Utopia Type: Level 2
• Typical Operating Supply Voltage: 1.8|3.3 V
• Minimum Operating Supply Voltage: 1.71|3.135 V
• Maximum Operating Supply Voltage: 1.89|3.465 V
• Maximum Output Rate: 8.192 Mbps

1.9
IMA line loopback is provided as shown in
the IMA block. The loopback is functional both when the serial/interleaved (TC enabled) is selected and when the
PHY side UTOPIA interface (TC bypass) is selected. When this loopback is selected, incoming receive data
continues through the IMA processor and is looped back out of the transmit interface.
Figure 1-14. IMA Line Loopback
1.10
IMA system loopback is provided as shown in
interface in the IMA block. When this loopback is selected, incoming transmit system data is looped back after IMA
processing and continues out the PHY side interface. The loopback is functional regardless of which PHY side
interface mode is selected. There are two different modes of system loopback, IMA System Loopback 0 and IMA
System loopback 1.
1.10.1
During IMA System Loopback 0, data is looped back at the PHY Layer UL2 Interface. The TxClav signals from the
PHY (TC or External) are used for handshaking and data is passed through the TC Block to the serial interface (if
the TC block is enabled) or is routed to the PHY side UTOPIA Interface (if the TC block is disabled).
28529-DSH-001-K
INTERFACE
ATM-SIDE
IMA Line Loopback
IMA System Loopbacks
IMA System Loopback 0
Internal
512Kx8
SRAM
IMA clocks
0
i
memory interface
Differential Delay
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Rx Block and
Tx Block and
extmemsel pin
Passthrough
Passthrough
Engine
IMA
External Memory
Interface Pins
Figure
1
INTERFACE
Figure
EXT RAM
JTAG
1-14. This loopback occurs in the PHY layer UTOPIA interface of
IMA
INTERFACE
JTAG
1-15. This loopback occurs in the PHY layer UTOPIA
Interface Pins
Micro
Counters
INTERFACE
TC
®
MICRO
OneSec
TC PORTS
TC Status
Registers
Cell processor
Cell processor
Cell processor
Cell processor
Clocks
Micro
Line interface 30
Line interface 31
Line interface 0
Line interface 1
TC Control
Registers
Functional Description
INTERFACE
PHY-SIDE
68