M28529G-12 Mindspeed Technologies, M28529G-12 Datasheet - Page 177

• Manufacturer Part Number: M28529G-12
• Description: ATM IMA 8.192Mbps 1.8V/3.3V 484-Pin BGA
• Manufacturer: Mindspeed Technologies

Specifications of M28529G-12

• Package: 484BGA
• Utopia Type: Level 2
• Typical Operating Supply Voltage: 1.8|3.3 V
• Minimum Operating Supply Voltage: 1.71|3.135 V
• Maximum Operating Supply Voltage: 1.89|3.465 V
• Maximum Output Rate: 8.192 Mbps

2.2.20
The TXIDL4 register contains the fourth byte of the Transmit Idle Cell Header. (See 0x14—TXIDL1.)
2.2.21
The RXHDR1 register contains the first byte of the Receive Cell Header. The header values direct ATM cells to the
UTOPIA port if an incoming ATM cell header matches the value in the header register. Receive Header Mask
Registers further qualify ATM cell reception. This header consists of 32 bits divided among four registers.
28529-DSH-001-K
Bit
Bit
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Default
Default
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0x17—TXIDL4 (Transmit Idle Cell Header Control Register 4)
0x18—RXHDR1 (Receive Cell Header Control Register 1)
TxIdl4[7]
TxIdl4[6]
TxIdl4[5]
TxIdl4[4]
TxIdl4[3]
TxIdl4[2]
TxIdl4[1]
TxIdl4[0]
RxHdr1[7]
RxHdr1[6]
RxHdr1[5]
RxHdr1[4]
RxHdr1[3]
RxHdr1[2]
RxHdr1[1]
RxHdr1[0]
Name
Name
Mindspeed Proprietary and Confidential
Mindspeed Technologies
These bits hold the Transmit Idle Cell Header values for Octet 4 of the outgoing cell.
These bits hold the Receive Header values for Octet 1 of the incoming cell.
VCI bits
Payload-type bits
Cell Loss Priority bit
®
Description
Description
Registers
162