M28529G-12 Mindspeed Technologies, M28529G-12 Datasheet - Page 125

• Manufacturer Part Number: M28529G-12
• Description: ATM IMA 8.192Mbps 1.8V/3.3V 484-Pin BGA
• Manufacturer: Mindspeed Technologies

Specifications of M28529G-12

• Package: 484BGA
• Utopia Type: Level 2
• Typical Operating Supply Voltage: 1.8|3.3 V
• Minimum Operating Supply Voltage: 1.71|3.135 V
• Maximum Operating Supply Voltage: 1.89|3.465 V
• Maximum Output Rate: 8.192 Mbps

1.15.1.2.3
When an interrupt occurs on the MicroInt* pin (pin AA1), it could have been generated by any of 385 events. The
M2852x’s interrupt indication structure ensures that no more than a maximum of seven register reads are needed
to determine the source of an interrupt. The interrupt is traced back to its source using the following steps:
1. Read the SUMPORT0-3 registers and the ONESECINT register to see which port(s) shows an interrupt and/or
2. Read the appropriate SUMINT register to see which bit(s) shows an interrupt.
3. If necessary, read the appropriate TXCELLINT or RXCELLINT register.
All Level 1 bits are cleared when the register is read. Once the register is read, ALL bits in that register are reset to
their default values. Therefore, interrupt service routines must be designed to handle multiple interrupts in the
same registers. In Level 2, OneSecInt and ExInt are cleared when the register is read. However, the TxCellInt and
RxCellInt bits are cleared only when the corresponding Level 1 register is read and cleared. Level 3 bits are cleared
when the entire corresponding Level 2 register has been read and cleared.
28529-DSH-001-K
whether there was a one second interrupt.
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Bit 0, RxCellInt, reflects activity in the RXCELLINT register.
Bit 1, TxCellInt, reflects activity in the TXCELLINT register.
Bits 2–7 are reserved.
Interrupt Servicing
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Functional Description
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