M28529G-12 Mindspeed Technologies, M28529G-12 Datasheet - Page 201

• Manufacturer Part Number: M28529G-12
• Description: ATM IMA 8.192Mbps 1.8V/3.3V 484-Pin BGA
• Manufacturer: Mindspeed Technologies

Specifications of M28529G-12

• Package: 484BGA
• Utopia Type: Level 2
• Typical Operating Supply Voltage: 1.8|3.3 V
• Minimum Operating Supply Voltage: 1.71|3.135 V
• Maximum Operating Supply Voltage: 1.89|3.465 V
• Maximum Output Rate: 8.192 Mbps

2.3.17
2.3.18
28529-DSH-001-K
Bit
Bit
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Default
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0xF12—TCCTRL2 (TC Control Register for TC ports 8-11)
0xF13—TCCTRL3 (TC Control Register for TC ports 12-15)
IhTxDatShft2
IhTxClkPol2
IhRxClkPol2
EnIH2
EnFrac[11]
EnFrac[10]
EnFrac[9]
EnFrac[8]
IhTxDatShft3
IhTxClkPol3
IhRxClkPol3
EnIH3
EnFrac[15]
EnFrac[14]
EnFrac[13]
EnFrac[12]
Name
Name
Mindspeed Proprietary and Confidential
Mindspeed Technologies
When set to 1, the Tx data on the Interleaved Highway Data Bus 2 will be output 1/2 IHTxClk2
cycle later than when the Tx inputs are sampled. Set to 0 to disable 1/2 cycle shift.
Interleaved Highway Bus 2 Tx Clock Polarity. Set to 0 for rising edge of IHTxClk2, set to 1 for
falling edge.
Interleaved Highway Bus 2 Rx Clock Polarity. Set to 0 for rising edge of IHRxClk2, set to 1 for
falling edge.
When set, this bit enables interleaved highway interface for TC Ports 8-11.
When set, this bit enables fractional T1/E1 logic for TC port 11.
When set, this bit enables fractional T1/E1 logic for TC port 10.
When set, this bit enables fractional T1/E1 logic for TC port 9.
When set, this bit enables fractional T1/E1 logic for TC port 8.
When set to 1, the Tx data on the Interleaved Highway Data Bus 3 will be output 1/2 IHTxClk3
cycle later than when the Tx inputs are sampled. Set to 0 to disable 1/2 cycle shift.
Interleaved Highway Bus 3 Tx Clock Polarity. Set to 0 for rising edge of IHTxClk3, set to 1 for
falling edge.
Interleaved Highway Bus 3 Rx Clock Polarity. Set to 0 for rising edge of IHTxClk3, set to 1 for
falling edge.
When set, this bit enables interleaved highway interface for TC Ports 12-15.
When set, this bit enables fractional T1/E1 logic for TC port 15.
When set, this bit enables fractional T1/E1 logic for TC port 14.
When set, this bit enables fractional T1/E1 logic for TC port 13.
When set, this bit enables fractional T1/E1 logic for TC port 12.
®
Description
Description
Registers
186