M28529G-12 Mindspeed Technologies, M28529G-12 Datasheet - Page 53

• Manufacturer Part Number: M28529G-12
• Description: ATM IMA 8.192Mbps 1.8V/3.3V 484-Pin BGA
• Manufacturer: Mindspeed Technologies

Specifications of M28529G-12

• Package: 484BGA
• Utopia Type: Level 2
• Typical Operating Supply Voltage: 1.8|3.3 V
• Minimum Operating Supply Voltage: 1.71|3.135 V
• Maximum Operating Supply Voltage: 1.89|3.465 V
• Maximum Output Rate: 8.192 Mbps

Table 1-9.
1.5.2
Figures 1-9
are listed in
Figure 3-33
CMOS integrated circuit packaged in a 484-pin PBGA. All unused input pins should be connected to ground or
power. Unused output and bidirectional pins should be left unconnected.
28529-DSH-001-K
Footnote:
(1) All unused inputs should be tied to ground or left unconnected. All unused outputs or bidirectional pins should be left unconnected.
VSS
(Continued)
VGG
Pin Label
and
Table
is the pinout diagram for the M28529 when operating in the UTOPIA-to-UTOPIA mode. It is a single
M28529 Pin Descriptions (19 of 19)
1-10
NOTE:
1-11.
Pin Diagram and Definitions (UTOPIA-to-UTOPIA Configuration)
illustrate the logic and block diagrams of the M2852x’s functional modules. Pin descriptions
Ground
(Continued)
Electrostatic Discharge
(ESD) Supply Voltage
Spare Pins
Signal Name
UTOPIA-to-UTOPIA configuration is selected by tying the PhyIntFcSel pin low.
When using the M28525/9 in Utopia to Utopia configuration, in addition to the standard Utopia Level 2
specification definitions, the device uses the PHY side RX and TX CLAV signals for the following purpose:
- The PHY TX CLAV signals are used to determine the stuffing rate for SICP cells. The M28525/9 will monitor
the CLAV signal to determine the fullness of the downstream device's Utopia FIFO.
- For applications where timing is not available from the RX_TRLs (such as DSL), the M28525/9 can be
configured to use the PHY RX CLAV signals to generate a clock that approximates the payload timing. As such,
the expectation is the RX CLAV signals from the TC/PHY layer approximates an ideal PHY layer device in the
sense that cell boundary times present on the receive physical bus are reproduced with a fixed offset in time to
the cells available on the PHY Utopia bus.
Contact Mindspeed applications engineering for more details.
Mindspeed Proprietary and Confidential
Mindspeed Technologies
AA22
AB13
AB21
AB22
AC24
AC23
AA23
AB23
AC05
AC25
AE15
AD3
No.
U13
U14
AA5
AB5
AB6
A25
T13
T14
T15
T16
D4
B1
I/O
Ground connections.
Provides ESD protection when interfacing with 5 V systems. If
using this device in a system with 5 V logic, this pin must be
connected to 5 V. If using 3.3 V system, connect to 3.3 V.
Spare (unused) pins on the package. Reserved for future use and
should be left unconnected.
®
Description
Functional Description
38