M28529G-12 Mindspeed Technologies, M28529G-12 Datasheet - Page 133

• Manufacturer Part Number: M28529G-12
• Description: ATM IMA 8.192Mbps 1.8V/3.3V 484-Pin BGA
• Manufacturer: Mindspeed Technologies

Specifications of M28529G-12

• Package: 484BGA
• Utopia Type: Level 2
• Typical Operating Supply Voltage: 1.8|3.3 V
• Minimum Operating Supply Voltage: 1.71|3.135 V
• Maximum Operating Supply Voltage: 1.89|3.465 V
• Maximum Output Rate: 8.192 Mbps

Table 2-9
been sized to ensure against saturation within a one-second interval. Therefore, when one-second latching is
enabled, the counters are read and cleared before they can saturate. All counters are cleared when read.
Table 2-9.
Table 2-10
Table 2-10.
28529-DSH-001-K
Address
Port Offset
0x800
0x801
0x802
0x803
0x804
0x805
0x806
0x807
0x808
0x809
0x80a
0x80b
0x80c
0x80e
0x810
0x80f
Address
0x30
0x31
0x33
0x34
0x35
0x37
0x38
0x39
0x3B
0x3C
0x3D
lists the M2852x’s counters. When the counters fill, they saturate and do not roll over. The counts have
lists IMA control and status information.
IMA_VER_1_CONFIG
IMA_VER_2_CONFIG
IMA_SUBSYS_CONFIG
IMA_MISC_STATUS
IMA_MISC_CONFIG
IMA_MEM_LOW_TEST
IMA_MEM_HI_TEST
IMA_MEM_TEST_CTL
IMA_MEM_TEST_DATA
IMA_LNK_DIAG_CTL
IMA_LNK_DIFF_DEL
IMA_RCV_LNK_ANOMALIES
IMA_PHY_LOOPBACK
IMA_DIAG_XOR_BIT
IMA_DIAG
IMA_TIM_REF_MUX_CTL_ADDR
IDLCNTL
IDLCNTH
LOCDCNT
TXCNTL
TXCNTH
CORRCNT
RXCNTL
RXCNTH
UNCCNT
NONCNTL
NONCNTH
Counters
IMA Control and Status Registers (1 of 33)
Name
Name
Idle Cell Receive Counter [Low Byte]
Idle Cell Receive Counter [High Byte]
LOCD Event Counter
Transmitted Cell Counter [Low Byte]
Transmitted Cell Counter [High Byte]
Corrected HEC Error Counter
Received Cell Counter [Low Byte]
Received Cell Counter [High Byte]
Uncorrected HEC Error Counter
Non-matching Cell Counter [Low Byte]
Non-matching Cell Counter [High Byte]
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Mindspeed Technologies
Device Version I
Device Version II
Configuration Control
Miscellaneous Status
Miscellaneous Control
Memory Test Address
Memory Test Address
Memory Test Control
Memory Test Data
Link Diagnostic Control
Link Differential Delay
Receive Link Anomalies
IMA Phy Side UTOPIA Loopback
Address Diagnostic
Diagnostic Register
TRL Control Address
Description
®
Description
Registers
Number
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Number
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Page
118