M28529G-12 Mindspeed Technologies, M28529G-12 Datasheet - Page 189

• Manufacturer Part Number: M28529G-12
• Description: ATM IMA 8.192Mbps 1.8V/3.3V 484-Pin BGA
• Manufacturer: Mindspeed Technologies

Specifications of M28529G-12

• Package: 484BGA
• Utopia Type: Level 2
• Typical Operating Supply Voltage: 1.8|3.3 V
• Minimum Operating Supply Voltage: 1.71|3.135 V
• Maximum Operating Supply Voltage: 1.89|3.465 V
• Maximum Output Rate: 8.192 Mbps

2.2.44
The IDLCNTH counter tracks the number of received cells. The counter is cleared on read.
2.2.45
This counter tracks the number of times that cell delineation was lost. Note that the LOCD interrupt is a dual event
interrupt and is set when cell delineation is lost or regained. Thus the number of LOCD events will not match the
number of LOCD interrupts.
28529-DSH-001-K
Bit
Bit
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Default
Default
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0x31—IDLCNTH (Idle Cell Receive Counter [High Byte])
0x33—LOCDCNT (LOCD Event Counter)
IdleCnt[15]
IdleCnt[14]
IdleCnt[13]
IdleCnt[12]
IdleCnt[11]
IdleCnt[10]
IdleCnt[9]
IdleCnt[8]
LOCDCnt[7]
LOCDCnt[6]
LOCDCnt[5]
LOCDCnt[4]
LOCDCnt[3]
LOCDCnt[2]
LOCDCnt[1]
LOCDCnt[0]
Name
Name
Mindspeed Proprietary and Confidential
Mindspeed Technologies
Received cell counter bit 15.
Received cell counter bit 14.
Received cell counter bit 13.
Received cell counter bit 12.
Received cell counter bit 11.
Received cell counter bit 10.
Received cell counter bit 9.
Received cell counter bit 8.
LOCD Event counter bit 7 (MSB).
LOCD Event counter bit 6.
LOCD Event counter bit 5.
LOCD Event counter bit 4.
LOCD Event counter bit 3.
LOCD Event counter bit 2.
LOCD Event counter bit 1.
LOCD Event counter bit 0 (LSB).
®
Description
Description
Registers
174