M28529G-12 Mindspeed Technologies, M28529G-12 Datasheet - Page 122

• Manufacturer Part Number: M28529G-12
• Description: ATM IMA 8.192Mbps 1.8V/3.3V 484-Pin BGA
• Manufacturer: Mindspeed Technologies

Specifications of M28529G-12

• Package: 484BGA
• Utopia Type: Level 2
• Typical Operating Supply Voltage: 1.8|3.3 V
• Minimum Operating Supply Voltage: 1.71|3.135 V
• Maximum Operating Supply Voltage: 1.89|3.465 V
• Maximum Output Rate: 8.192 Mbps

Functional Description
1.15.1.2.2
Interrupts
The M2852x’s interrupt indications can be classified as either single- or dual-event; a single-event interrupt is
triggered by a status assertion; a dual-event interrupt is triggered by either a status assertion or deassertion. Both
types of interrupts are further described in the following examples.
Single-event interrupt: When a parity error occurs on the UTOPIA transmit data bus, an interrupt is generated on
ParErrInt, bit 7, in the TXCELLINT register (0x2C). This bit is cleared when read.
Dual-event interrupt: When LOCD occurs, bit 7 of the corresponding RXCELLINT register (0x0D) is set to 1. This
bit is cleared when the register is read. Once cell delineation is recovered, bit 7 is set to 1 again, generating
another interrupt.
All interrupt bits have a corresponding enable bit. This allows software to disable or mask interrupts as required.
NOTE:
The IMA block does not generate interrupts.
The M2852x uses three levels of interrupt indications. The first level consists of receive or transmit interrupt
indications, which correspond to specific events on a specific port. The second level summarizes first level
interrupts and indicates framer and one-second interrupts for each port. The third level indicates which port
generated an interrupt.
The first level interrupt indications are located in registers TXCELLINT and RXCELLINT for each port. Each
interrupt bit in these registers can be disabled in the corresponding ENCELLR or ENCELLT register, respectively.
The result is then ORed into the appropriate bit in the port’s SUMINT register.
The second level consists of summary interrupt indications, located in the SUMINT register. It also includes the
OneSecInt and the ExInt indications. Each interrupt bit in these registers can be disabled in the corresponding
ENSUMINT register. The result is then ORed into the appropriate bit in the SUMPORT register.
The third level contains the overall interrupt indications for each port in the SUMPORT register. These bits can be
disabled in the ENSUMPORT register. The result is ORed to the MicroInt* pin. The MicroInt* pin can be enabled or
disabled by setting the EnIntPin (bit 3) in the GENCTRL register (0x0F00).
Figure 1-42
illustrates the flow chart of the interrupt generation process and
Figure 1-43
illustrates the registers
involved in the interrupt generation process.
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