PXAH40KFBE NXP Semiconductors, PXAH40KFBE Datasheet - Page 35
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PXAH40KFBE
Manufacturer Part Number
PXAH40KFBE
Description
Manufacturer
NXP Semiconductors
Datasheet
1.PXAH40KFBE.pdf
(42 pages)
Specifications of PXAH40KFBE
Cpu Family
XA
Device Core
80C51
Device Core Size
16b
Frequency (max)
30MHz
Interface Type
USART
Program Memory Type
ROMLess
Program Memory Size
Not Required
# I/os (max)
32
Number Of Timers - General Purpose
2
Operating Supply Voltage (typ)
3.3/5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
2.97V
Instruction Set Architecture
CISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
100
Package Type
LQFP
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PXAH40KFBE
Manufacturer:
TriQuint
Quantity:
1 200
Part Number:
PXAH40KFBE
Manufacturer:
NXP/恩智浦
Quantity:
20 000
Company:
Part Number:
PXAH40KFBE,557
Manufacturer:
NXP Semiconductors
Quantity:
10 000
Philips Semiconductors
1999 Sep 24
Single-chip 16-bit microcontroller
Note:
OE, BLE, CS
Clkout
D[7:0]
On all cycles on 8-bit bus, BHE remains high (inactive)
Note:
WARNING: Some 8-bit I/O devices (especially FIFOS) cannot operate correctly with 2 bytes being read for a one byte read. The most common (and least expensive)
solution is to operate these 8-bit devices on a 16-bit bus, and access them in software on all odd byte (or all even byte) boundaries. An added benefit of this tech-
nique is that byte reads are faster than on an 8-bit bus, because only 1 word is fetched (a single read) instead of 2 consecutive bytes.
BHE remains high (inactive) for all accesses on an 8-bit bus. A burst code fetch can be
from 1 to 8 words (1 word = 2 bytes), a 2 word fetch is shown here.
On the external bus, ALL XA-H4 reads are 16-bit reads. If the CPU instruction only specifies 8-bits, then the CPU uses the appropriate byte, and discards the
extra byte. Thus, “8-Bit Reads” and “16-Bit Reads” appear to be identical on the bus. On an 8-bit bus, this will appear as two consecutive 8-bit reads even
though the CPU will only use one of the two bytes.
t
CHAV
A19 – A1
D7 – D0
ClkOut
BLE
CS
OE
A0
Figure 14. Generic (SRAM, Flash, I/O Device, etc.) Read (16-Bit or 8-Bit) on 8-Bit Bus
Even Address
Driven by XA
Note 3
t
CHAV
Figure 15. Burst Code Fetch on 8-Bit Bus, Generic Memory
t
AVSL
t
DIS
LS Byte
t
CHSL
Note 3
Note 2
t
DIH
t
CHAV
Address + 1
t
DIS
t
DIS
MS Byte
35
Note 2
Note 2
t
DIH
t
CHAV
t
CHAV
Address + 2
t
CHSH
t
t
DIS
DIS
LS Byte
Note 2
t
Note 2
DIH
t
DIH
t
CHAV
Address + 3
t
OHDE
Driven by XA
t
DIS
MS Byte
t
AHDR
Note 2
Preliminary specification
t
DIH
t
CHSH
XA-H4
SU01245
SU01283