PXAH40KFBE NXP Semiconductors, PXAH40KFBE Datasheet - Page 10

• Manufacturer Part Number: PXAH40KFBE
• Manufacturer: NXP Semiconductors

Specifications of PXAH40KFBE

• Cpu Family: XA
• Device Core: 80C51
• Device Core Size: 16b
• Frequency (max): 30MHz
• Interface Type: USART
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• # I/os (max): 32
• Number Of Timers - General Purpose: 2
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.97V
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 100
• Package Type: LQFP
• Lead Free Status / Rohs Status: Compliant

Philips Semiconductors
CONTROL REGISTER OVERVIEW
There are two types of control registers in the XA-H4, these are SFRs
(Special Function Registers), and MMRs (Memory Mapped Registers.)
The SFR registers, with the exception of MRBL, MRBH, MICFG, BCR,
BRTH, BRTL, and RSTSRC are the standard XA core registers. See
WARNINGs about BCR, BRTH, and BRTL in Table 2.
SFRs are accessed by “direct addressing” only (see IC25 XA User
Manual for direct addressing.) The MMRs are specific to the XA-H4
Table 2. Special Function Registers (SFR)
1999 Sep 24
BCR
BTRH
BTRL
MRBL#
MRBH#
MICFG#
CS
DS
ES
IEH*
IEL*
IPA0
IPA1
IPA2
IPA3
IPA4
IPA5
IPA6
IPA7
P0*
P1*
P2*
P3*
Single-chip 16-bit microcontroller
Name
Bus Configuration Reg
RESERVED – see
Warning
Bus Timing Reg High
Bus Timing Reg Low
MMR Base Address Low
MMR Base Address High
ClkOut Tri-St Enable
1 = Enabled
Code Segment
Data Segment
Extra Segment
Interrupt Enable High
Interrupt Enable Low
Interrupt Priority A0
Interrupt Priority A1
Interrupt Priority A2
Interrupt Priority A3
Interrupt Priority A4
Interrupt Priority A5
Interrupt Priority A6
Interrupt Priority A7
Port 0
Port 1
Port 2
Port 3
Description
46Ah
469h
468h
496h
497h
499h
443h
441h
442h
427h
426h
4A0h
4A1h
4A2h
4A3h
4A4h
4A5h
4A6h
4A7h
430h
431h
432h
433h
Address
SFR
WARNING – Never write to the BCR register in the XA-H4 – it is initialized to 07h,
the only legal value. This is not the same as for some other XA derivatives.
WARNING – Immediately after reset, always write BTRH = 51h, followed by
writing BTRL = 40h in that order Follow these two writes with five NOPS This is
writing BTRL = 40h in that order. Follow these two writes with five NOPS. This is
not the same as for some other XA derivatives.
EHSWR3
MA15
MA23
MSB
33F
337
387
38F
397
39F
EA
–
–
–
–
–
–
–
–
EHSWR2
EDMAH
MA14
MA22
33E
38E
39E
336
386
396
–
Reserved
10
PHSWR1
PHSWR3
EHSWR1
EDMAL
PDMAL
PSC23
MA13
MA21
on-chip peripherals, and can be accessed by any addressing mode
that can be used for off-chip data accesses. The MMRs are
implemented in a relocatable block. See the “Memory Controller”
chapter in the XA-H4 User Manual for details on how to relocate the
MMRs by writing a new base address into the MRBL and MRBH
(MMR Base Low and High) registers.
33D
PT0
PT1
38D
39D
335
385
395
–
–
Bit Functions and Addresses
EHSWR0
MA12
MA20
33C
EX2
38C
39C
334
384
394
–
MA19
33B
ET1
38B
39B
333
383
393
–
–
–
–
–
–
–
–
–
–
–
MA18
EAuto
33A
EX1
38A
39A
332
382
392
–
–
PHSWR0
PHSWR2
PDMAH
PSC01
PAutoB
MA17
ESC23
PX0
PX1
PX2
ET0
339
331
381
389
391
399
–
–
Preliminary specification
CLKOE
MRBE
MA16
ESC01
LSB
EX0
338
330
380
388
390
398
XA-H4
Reset
Value
EFh
FFh
FFh
FFh
FFh
FFh
07h
x0h
01h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
xx